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Yes, the ROM does it via the TT registers; I assume the system does the same later on when it takes over. No, it was never planned for or supported; the DeclRom were designed for NuBus and so only for devices, not memory. All Macs assume the only memory controller in the system is the built-in...

Those two are sort of linked. I don't think the MC68030 will do burst to non-cacheable pages, which is how the framebuffer is set up (and the Quadra cheats, as the internal framebuffer is set to non-serialized while any PDS device is set to serialized, but that's off-topic). If you don't intend...

Thinking about it, not sure DMA is possible with a mutiplexed design. If the memory controller doesn't register the address signals (and with a '020/'030 it has no reason to), then you need both the address and data at the same time on the bus. I think.

Not that I know of, but the PDS slot in the LC475 is using the interface from the MC68030, it's identical to that in the LCIII and backward compatible to the shorter, less capable slot in the LC and LCII. There is a modern Ethernet card for the SE/30, the SEthernet/30. I have reworked my own...

If you need a level switcher (the IRQ will be pulled up to 5V), then you can use a silicon switch as a shifter and a physical switch to control the silicon switch (or if you don't mind the extra noise on the signal, just send the IRQ through the physical switch!). Just one FPGA pin but 2 or 3...

Unsupported :-) In practice, stackable cards tend to have switches to choose the slot/irq. It's not very clean nor macintosh-like, but it worked. Apple only ever intended for one card to be used; I suspect in the SE/30 the idea was that a single card could have multiple functions in multiple...

The older systems are not very well protected or architectured, so ultimately you can do almost anything... but it's a lot easier and safer (in terms of SW compatibility) to stick to Apple's rules. The "normal" way is to use the memory range(s) and associated IRQ, as were originally defined for...

Beware the pseudo-slot range is "associated" to an IRQ (loosely, but it's easier to do the SW when respecting it), as those you're supposed to use are connected to a VIA - you're not supposed to use /IPL[2..0] directly, only IRQ[3..1]. The unused one should be high-Z to play nice with other...

Oups, sorry http://www.bitsavers.org/components/idt/_dataBooks/1991_IDT_SRAM_Databook.pdf http://www.bitsavers.org/components/ti/_dataBooks/1990_TI_Cache_Memory_Management_Data_Book.pdf Enhancing MC68030 performance using the SN74ACT2155 cache. It might be easier to use synchronous mode on...

In case you didn't know - the MC68030UM has a section "12.5 Static RAM memory Banks" that can be interesting for this use case. Also, manufacturers of cache tag SRAMs had application notes with detailed timing requirements for higher-speed MC68030 (some links here). A SRAM memory bank is just a...

Spectacularly ignorant BS at that. The MC68120 actually exists, and it's not exactly a high-performance successor to the MC680x0: 1984 databook, so at least as old as that.

Lack of demand I presume, silicon is still in production but is expensive (e.g. PI7C9X130DNDE, which can do both way).

Costs for entry-level FPGAs and PCB manufacturing has gone way done over the years. I just did a trial quote at JLCPCB for a 6-layers board (with 0.2/.35 via-in-pad and double-sided assembly, far from the cheapest option!) with an onboard smallish Artix-7 (50T-1) + DDR2, and it was less than...

Physically the pinout is different, but logically it's equivalent to the IIsi/SE/30 (except it's 25/33 MHz in the LCIII/III+instead of 20/16). So a different board is required, but the gateware will need a new pinlist at most and the software can be the same. EDIT: oups, I was thinking of the...

You found the NubusFPGA, but some answers that may not be in the repo: Unless you need a specific feature of the FPGA (like 7-series' TMDS signalling for HDMI), I'd say * Toolchain you're accustomed to for design, synthesis & simulation * Package complexity/number of pins; 1.0mm pitch BGA are...

Absolutely. The '040 had a lot of improvement over the '030, including the caches and faster/better bus interface. The computational part was also a bit refined over a clock-doubled '030, as mentioned in the extract I posted. Unfortunately, most of Motorola's academic communication on the...

Mmmm, Wikipedia insists that my memory has failed me and it was 3x33 and 2x50, but no 4x. And Wikipedia happens to be correct - though it's too late to fix my post. Here's the evidence from the '486 DX4 datasheet: I guess it was the 25 and 33 MHz motherboard that were shared; as I mentioned...

It can do both, the fastest ones (DX4-100) could do either 25x4 or 33x3. They usually ended up doing 25x4 because same chip, same marketing, cheaper board, and you could do 25x3 with the slower variant (DX4-75) on the same motherboard. You wanted them to do 3x at nominal speed as that meant a...

Not really a scam. Marketing needs and all-around misunderstanding of how CPU works I'd say. WayWayTL;DR: That, and see the last few paragraphs, after all the long historical and near-technical ramblings. It's the same issue as the whole "that's an 8-bits computer and that's a 16-bits computer...

There was support added, as documented in "Designing PCI Cards and Drivers for Power Macintosh Computers" (p513). However, I have never seen the relevant status/control codes called on any 68K version of the system I've tried :-( Similar to X11; the Mac is much more simple - an application can...