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The blue box from China arrived, aaaand... reading the latched data register works! Funny what making everything (a bit) less spaghetti-like will do. I think I might end up ready to test this in an actual Mac soon... at which point I'll find out whether this heckin' chonker of a three-board...

While I wait for my PCBs, I've been trying to see what I can fit in a single 1504, and I seem to have arrived at a design that will (in cooperation with a PIC) simulate an IWM with two 800 kB floppy drives... but still no DCDs. I had logic to support them initially, along with a rather nice...

Way ahead of you. =) If you see any topic that isn't there, do let me know, I'm definitely interested in knowledge sharing. Yeah, that's the impression I get as well. Microchip's "ProChip Designer" (seemingly a legacy of Atmel) comes with an HDL synthesizer of some kind, but it doesn't seem...

Warning, semi-coherent rambling ahead. I'm stuck for a moment on the two-1504 IWM clone, I believe my abominable wiring job to be at fault for some glitches I've been seeing: Basically every time I started toggling the !DEV line to imitate the Mac polling the data registers, I started seeing...

I wouldn't suspect any trouble with that, but I'm not really enough of an electrical engineer to say for sure. As for the VIA versus the WDC replacement... it's a data point, I'm not sure why one would work and not the other, but if you're able to swap them, that might be a good experiment.

I don't think so. As far as I'm aware, ghofbauer's change was just to switch the PIC's config to use an external clock source and divide it in half so it had the same instruction clock rate as the original. If you're seeing 1.6 MHz into the PIC, that should be it. I'm lacking context, what...

I've got nothing, I'm afraid. =/ To the best of my knowledge, the instruction clock is the only thing that should be different between the real thing and the PIC16F88/87 adaptation. If I had a better understanding of the code and the affected machine to test with and a whole load of free...

I haven't, actually... don't know my way around that source tree too well, but maybe will dig a little and see if I notice anything obvious. I no longer think it's realistic to do this in one 1504, I keep bumping my head against the macrocell limit. Going to try two like I originally...

My understanding of the IWM spec (and the Disk II) continues to evolve, albeit slowly. In the Disk II, Q3 (2 MHz, twice the clock frequency of the Apple II) is the only clock that exists, so it's used for everything. In the IWM, Q3 is only used for writing data in synchronous mode, FCLK (in...

Aha, you're right. Must be because Apple knew they'd be offering the FDHD upgrade. Maybe I can do some experimentation on my pre-FDHD SE...

Am realizing that it will be at least useful and at most necessary for me to get an actual IWM to test with... ideally a test machine with a ZIF socket where the IWM should be, too. Guessing I'll just have to keep my eyes peeled for someone selling a Plus or earlier in good condition (not sure...

I wish I understood better what the "latch mode" bit in the IWM was for. Apparently the latch mode bit "should" be set in async mode, but the spec sheet also says "In port operation, which is asynchronous mode true and latch mode false with /DEV held low indefinitely, read data will appear...

If you're interested, I'd grab Quartus II 13.0sp1 before Intel takes it down (they're real jerks about keeping downloads available), that's the last version that supports the MAX7000 series with which the Atmel 150x chips are compatible.

Well, I spent an interesting morning teaching myself Verilog and translating my CUPL design into it, and... success! The clock generator side of the IWM appears to be working perfectly. There's more to do, of course, but this is a big step and definitely proves out the workflow of using...

I think you understand more or less correctly, yes, though the IWM's WRDATA output actually toggles to represent ones, as differentiated from the RDDATA input, which interprets falling edges as ones. I'd be lying if I said I understood exactly why this is or what it translates to on the disk...

The input clocks are 2 MHz on Q3 and either 7 MHz or 8 MHz on FCLK (I don't believe FCLK existed in the Disk II, or at least, it wasn't used for bit cell timing). Q3 is only used in the synchronous mode for bit cell timing and eight periods of it in slow mode (4 µs) or four periods in fast mode...

The more I think about this, I am starting to wonder, maybe it would make more sense to target one 1508. I'm thinking that thanks to a fatal bug in the Atmel fitter, I might have to start over and implement this in Verilog instead of CUPL (which is going to be interesting as I don't actually...

No great reason, but two 1504s are actually cheaper than one 1508.

Hmm. Is it possible to throw newly-available SRAM of some kind in there, or does it have to be DRAM?

Oh, that raises an interesting question - are the necessary DRAM ICs available new, or do they have to be recovered from elsewhere?