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I've decided that the FPGA isn't really necessary if we bit-bang the signals out via a wide GPIO port. That should be faster since the data doesn't need to first be transferred over a slow connection from the processor to the FPGA. Since these processors in question run at basically GHz speeds...

The tree structure is supposed to generalize it to multiple models and memory maps. It can also be constructed in a way that it can double as a structure used for the 68030 MMU emulation. There has to be at least some MMU emulation. (forget 68020 + "Apple HMMU." We can build that on top of the...

Well I think what I described is technically a JIT, but the problem is that I haven't thought about adding the ability to interpret portions of code that have not yet been translated when the emulator encounters an untranslated jump destination or the end of a translated block. In that case, it...

The latest in a flurry of acquisitions. Hopefully it won't affect distributors' willingness to stock NXP's products. Microchip-Atmel is probably gonna suck in the long-term as well. Maybe I can eliminate the FPGA entirely and get a more expensive processor chip that has enough GPIO (and CPU...

Here is the command set I've designed for the FPGA-processor interface: Hopefully this will be at least a little clear.

Here's the block diagram of the QorIQ LS1012A: Kinda odd to use such a network-y processor, but it's cheap and it only has 211 pins, so it'll be easy to "fan out" all of the signals when it's on a board. All of the boards have to have at least 4 layers, by the way. Two-layer boards would not...

I have designed the basic architecture for an accelerator “system” which can be adapted to any 68k Macintosh with a PDS slot. The goals of the design were as follows: moderate cost at least 50x faster than Mac SE basic architecture can be used for any 68000, 68020, 68030 Mac with a PDS. Maybe...

Like I said, I know it will cost quite a bit of money to build the cards, though the Vampire for Amiga people price theirs at 150 EUR if I recall correctly. I'm gonna complete the project, release the design files and source code, and then make myself a website and put it and my few other major...

Well my thought was to do the translation in hardware and then write the instructions into the memory accessible by the ARM core, so the source for the software emulators would not be the most applicable. I think that will yield higher performance than the software emulator approach, and like I...

Hmm... should have trusted the part number. I thought that mislabeled '030 was for embedded applications and this was a faster compatible part or something. I have emailed the developer of the Apollo core for Amiga and he hasn't responded. Plus the concerns you bring up, Gorgonops, make it seem...

Wow, look at this: http://www.digikey.com/product-detail/en/freescale-semiconductor-nxp/MC68030FE16C/MC68030FE16C-ND/1167296 166 MHz 68030! !!!! I didn't know one existed that fast. Now that would make for a mean SE/30. '040s never went faster than 40 MHz. I still think that the soft-core route...

Not immediately, I don't think so. The caching strategy I articulated earlier was created with the SE/30's memory map in mind... I didn't consider NuBus, for example. I do know that the SE/30 PDS differs slightly from the PDS on other 68030 machines. However, only some '030 machines have a...

Well, the issue with PDS cards using DMA is that I wanted to max out the ram of the machine using the DDR2 cache. Cards designed for an SE/30 won't be able to operate at the 50 MHz bus speed of the accelerated CPU, so they need to go onto the main bus. But then there will be a problem if the...

Yes, I see now, techknight, after looking at some of the 68k timing diagrams. It doesn't look very hard to implement the synchronous bus. I meant that the synchronous peripheral bus seemingly cannot be stalled by the slave not asserting /DTACK like the asynchronous memory bus can be. I think...

Soldering is certainly not one of my skills... I have a friend who does my soldering, and I do his programming, haha. So I wouldn't want to suggest that you desolder the components. I will say, however, that neither the board nor the components strike me as particularly costly. The cost...

So in sum, my desire to make a halfway affordable (for me and everyone else haha) accelerator is in strong competition with my desire to over-design it and give it WiFi, Bluetooth, USB, fast ARM coprocessor, etc. Ain't nobody got time to implement all that anyway! Haha another CS or EE student...

Some costs depend on quantity, while others don't. I can't say exactly how much it will cost, but I'll break it down: PCB (printed circuit board): 6+ layer PCBs of good quality can be a bit costly in small volumes. To produce 10 6-layer boards of the right size might be $60 each. In quantities...

In this first post, I will articulate my vision of accelerator cards for the SE and SE/30. What follows is a bit verbose, but hopefully this proposal will lead us to a finished product. I plan to start developing this thing in a few months. Right now, I'm trying just to gather more information...

Cloning the board would be easy. Desolder all components, stick it on a scanner, then trace over the scanned image in your PCB layout program of choice. If someone can get me such an image, I'll do it and put it up on OSH Park.

I've got a product to finish, test, and ship, and then I'll set my sights on the accelerator board. If more details about the Xceed come up, I'll try my best to add compatible functionality to my accelerator. It should be easier with a big FPGA on the board that can handle some of both elements...