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I don't know why I feel happy about it, but for some reason Renesas still manufacture some variant of their "QSpan II" Processor-to-PCI Bus Bridge, which has native support for the 68040 bus. They are bit pricey though. Theoretically, one could build a PDS'040 <-> PCI bridge board to be able to...

There's only 6 visible 71256, which suggest to me the two hidden by labels are also 71256, distributed identically to the Flash on he other side. Random guess: SRAM storage of the code for warm reboot, flash storage for more lasting attempts? With just a buffer and some SRAM you can't do a lot...

Technically, the bitstream can be generated for other resolutions to match the display (1920x1080 is the maximum the FPGA can handle and so common on cheap HDMI LCDs it's a good default), but that resolution becomes the 'upper bound' and all lower resolutions are as you described window-boxed...

The carrier board itself was completely assembled by JLCPCB, other than the through-holes connectors (two 2x32 2,54mm pitch header, and the 140-pins KEL connector). Then you manually solder the 268 TH pins, that's the only manual step. @Jockelill had an extra step as in the first batch, there a...

One comment: you've dropped the mac ABi (passing values through registers) in favor of C (stack), but the '030 needs all the help it can get performance-wise. Once the code is stable, I'd suggest reinstating a register-based ABI wherever possible to save a bit on time, at least for function on...

For my *FPGA I picked CC BY-NC-SA 4.0 for the hardware (SW is straight GPL). The non-commercial part is not so much to avoid third-party making and selling the design, but as a safety net against being asked to support subpar copies sold by third-parties. If someone wanted to make and sell them...

Hardware-wise, there's no major problem. Just need some memory chips and an adequate memory controller mapped in the proper area, and some way to discriminate between the two maps so the new controller doesn't conflict with the onboard BBU, which is likely the most complex part. Software is the...

To simplify your life, rather than MacsBug, you can build a Mac console application that will do e.g. printf("0x%08x\n", *(int*)0xFE000000);. You can do that natively with CodeWarrior, or from a modern box with Retro68. Unlike modern operating system, this area is not protected from user access...

Maybe simply with a scanner as today, except likely SCSI. Those were available in B&W and color, though color was expensive. MacUser from Dec'88 has an advertisement for the JX-450 from Sharp at the low, low, price of ... "call" :) Other ads offer various scanners from several hundreds to...

I tend to agree. But if a zero-wait-state cache could be made by a FPGA/external SRAM combo (or even a small prototype using the FPGA for data as well), it could be built with some level of associativity rather than the pure direct mapping of the era. That might help a bit. And using modern SRAM...

Good question. If that faithfully recreate the behavior of the '040 bus, I don't see why the basic framebuffer wouldn't work. The acceleration is currently patching 68K QD, so that wouldn't work (it doesn't in the NuBusFPGA in a 7100 for instance, though the framebuffer itself work). From some...

I've looked for a similar solution to initialize the RAM disk in the NuBusFPGA, and then gave up and just fell back on the 'store an empty FS in the DeclRom and dump it onto the RAM disk'. It's just RLE-compressed and most of the data in the original HFS are just init values that are skipped to...

In fairness to Apple, /ECS is pretty useless. It doesn't qualify other signals (/AS mostly does, /DS for data... sometimes) and it can be asserted and then de-asserted without any actual cycle occurring. It's basically just a warning that the CPU might do an useful cycle soon... @croissantking...

Ouch. If that's needed for e.g. initialization or whatever, then that's probably too complex to recreate. Probably easier to work on a fast soft-core 68k with MMU.

I always wondered how they implemented the '030 and '040 PDS PPC acceleration. I wonder if anyone has tried to create schematics from those cards? Interfacing between the '030/'040 bus and the PPC is probably not obvious. There's currently no suitable re-implementation of '030/'040 (with the...

Congratulations! That's a huge result! I hadn't realized CLKOUT defaulted to 4 MHz. That means your timings must 'work' (even slowly) at 4 MHz so that the CPU can reprogram COCON to generate the 25 MHz clock, I suppose? Annoying chicken-and-egg problem :-) The IIfx PDS will run at an apparent...

As there is quite a bit of ADB knowledge on this forum, including for weird I/O, maybe you could kill two birds with one stone and use some form of ADB to both get some 5V power and control of the monitor ID? A small piece of software could read/write the needed value in some form of...

Hopefully you will figure it out. My first instinct was a timing issue (different behavior between registers and SRAM in practice), but if indirect accesses through registers are affected it can't be that... The fact you can talk to the ROM and the registers is definitely a win :-)

I suspect the big issue is, as usual, the software. Although it's not the most common types of emulation, that device should be able to connect to many 80's/90'/s AS/400, and those do have a community of enthusiasts. If the original hard disk is available, the software might be salvageable...

Hehe, quoting Wikipedia for the 5251: I can understand why someone would prefer a terminal emulation device in a Mac or PC rather than an extra 36 kg worth of kit :-)