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It is a nice CPU, and yes it's likely somewhat crippled by small caches - as most CPU would be, the L1 cache size being limited by area (almost any CPU without built-in L2) or by meeting L1 access latency requirements (almost everything since the introduction of the built-in L2). The 64-bits...

The MC88200 aren't CPUs, they are Cache/Memory Management Units for the MC88100 (the first implementation of the MC88000 architecture). The MC88100 doesn't have internal caches or MMU, aid it has two external 32-bits memory bus ("P-Bus"): one for instruction, one for data. Unifying that into a...

Multi-processor (either true SMP or some other schemes like the stuff implement in MP PPC machines under OS9) is mostly a software issue - you need the software to support it. And that means adapting the software to the quirks of the underlying hardware, and back in the days there was a lot of...

The documentation doesn't make it obvious in any one place, other sources are sometimes clearer. The important bit is a note right at the beginning of the UM in the preface: (emphasis mine). In the flowchart the negation of /DSACKx (or, in my case, /STERM) is also explicit, as it is in the...

Cost-cutting / didn't read the CPU manual properly (I'm betting the first!) Quoting from the '030 UM on asynchronous bus cycles: That's negate, not tri-state or deassert. The device should actively drive the signal to logic 0 (so +5V) before tri-stating for the next bus cycle, as relying on...

Ouch, that's one massive board for the SE/30 ! I see that in addition to the ATF1502, you switched the Flash from PLCC to TSOP - which means, it can't be socketed for out-of-board programming. I also see the write enable pin is connected to the CPLD; is the intention to do in-place programming...

Maybe some inputs to the GLU are damaged. Normally, to generate /FPU_CS, it needs all three FC lines and A[13..20]. If one or more of those is 'stuck' or unreliable, /FPU_CS would be affected. The address lines would probably cause additional issues, but I don't think FC is sued for anything...

Wouldn't "reliably bad" VRAM (as the boot screen would imply) not allow the display of a clear picture, ever? That's what puzzles me. At some point, the DAC reads good value from the VRAM and push them to the screen with no issue, and something has written the data in the VRAM reliably as well...

Turns out, the MMCM (clocking module) in the 7-series FPGA have a reconfiguration interface (see xapp888), that interface can be exposed by Litex, and there's already some codes out there using the interface. So changing the clock wasn't as difficult as I thought it would be, and the recent...

Is that an accelerated card? Is acceleration enabled? Try without if so. To me, the fact that the pictures are drawn fine suggest the CPU/DRAM -> VRAM path is fine, including the VRAM themselves. Same for the VRAM -> DAC -> video output path. But it seems than whenever the Mac does something...

Beware, that's not a fork from another design, that's my own and it's slightly different by being mostly SMD (surface mount) and having a switch to chose between soft-power and always-on (for Macs with a dodgy soft-power circuitry). You're welcome to build it for yourself (and others), but you...

That fake '882 works at 33 MHz? lucky you! Guess it was a "reliability issue with the FPU socket" after all :-)

I'll just quote my answer on reddit :)

Does it not check A[28..31] at all for slot ($F) vs. super-slot ($9-$E) area? In theory that's needed as otherwise the superslot area of other devices could be accidentally matched... (for instance the NuBusFPGA can map all of the on-board memory in the superslot area for the RAM disk). Not that...

NuBus isn't very complex, except for the multiplexed bus aspect that may requires latching the address. Burst mode is a bit more complex, and so is bus-mastering, but I wouldn't expect.a video card to need either. Burst isn't implemented by the host on Mac II and just as slave for Quadras, so...

You can try 'bending away' the problematic address pin (so they are no longer in the socket/PCB) and soldering them using some patch wire to low instead of high (or the reverse). if the chip is toast anyway, it doesn't risk much, you just have to make sure you don't short anything.

Forgot about those but yes, the assumption is sound isn't a critical feature so can be ignored in a first draft. And it's one of the thing for which I did write a driver (for HDMI audio), so there's a path to an alternate solution to add sound later.

Given the many discussions on capacitors replacement & the whole polymer vs. tantalum vs. ceramic, here's an interesting video I just discovered on the subject: James Lewis - They're JUST Capacitors Voltage impact on ceramic capacitance is also discussed in this article: Temperature and...

All the better. The II and IIx don't have subtle difference due to the slightly weird memories? The nice thing about the IIcx is that in addition to the simplicity, it's bog-standard FPM memory and I believe works out-ot-the-box with the the IIsi's 32-bit clean memory. If the Iix and SE/30 have...

(a) figure out what the chip is doing, and the required timings (b) recreate the functionality in some modern language (some form of verilog) (c) validate some key characteristics in simulation (d) validate in-situ with a FPGA (e) do the design and validatation of the ASIC itself (a) to (d) are...