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It works! On one combination of computer (IIsi) and monitor (Dell E151FP), anyway. This is the first time I've tested it with real hardware and not just a PIC I programmed to spit out simulated sync signals, and it passed with flying colors! I suppose the next thing to do is to knock together...

I did a rewrite of the code that profiles the composite sync signal and freed up a considerable amount of code space... I am now where I was before but hopefully a on a bit more solid ground. Going to have to do some more testing with real Macs and see whether my signals are precise enough for...

On second thought, don't. It's a neat little chip but experimentation reveals that it's missing too many features to do this job well. The 1501 will do much better. (And, failing this project, I already have a few others that it can be used for...)

Cool! Grab a PIC10F322 as well while you're about it, they're super cheap.

Thanks! I will definitely take you guys up on that once I get something a bit closer to shippable (though if you've got a PICkit3 or similar and feel like breadboarding, I'd be more than happy to work with you before that!) Interesting, thanks for the tip. I may do that - again, once I'm a...

I have a "syncing" feeling it's time for another TashProject... Introducing... TashSync! Elevator Pitch It's a video sync signal conversion/generation firmware for Macs, targeting the PIC12F1501 (8 pins, 77¢ in quantity) microcontroller. Primarily, it takes a "composite" video sync signal...

Well, I tried this approach with the 'north' 1504 code, to mixed success. Centralizing the tristate (along with hand-unrolling a generate block) got iverilog's V95 code generator to run successfully, but yosys still died, this time complaining of "multiple edge sensitive events found for this...

This is the kind of thing I'm doing: module handshake_register ( input wire underrun_n, input wire write_data_ready, input wire oe, inout wire [7:0] data ); assign data = oe == 1'b0 ? 8'bZZZZZZZZ : {write_data_ready, underrun_n, 5'b11111}; endmodule Then there are multiple...

The blue box from China arrived, aaaand... reading the latched data register works! Funny what making everything (a bit) less spaghetti-like will do. I think I might end up ready to test this in an actual Mac soon... at which point I'll find out whether this heckin' chonker of a three-board...

While I wait for my PCBs, I've been trying to see what I can fit in a single 1504, and I seem to have arrived at a design that will (in cooperation with a PIC) simulate an IWM with two 800 kB floppy drives... but still no DCDs. I had logic to support them initially, along with a rather nice...

Way ahead of you. =) If you see any topic that isn't there, do let me know, I'm definitely interested in knowledge sharing. Yeah, that's the impression I get as well. Microchip's "ProChip Designer" (seemingly a legacy of Atmel) comes with an HDL synthesizer of some kind, but it doesn't seem...

Warning, semi-coherent rambling ahead. I'm stuck for a moment on the two-1504 IWM clone, I believe my abominable wiring job to be at fault for some glitches I've been seeing: Basically every time I started toggling the !DEV line to imitate the Mac polling the data registers, I started seeing...

I wouldn't suspect any trouble with that, but I'm not really enough of an electrical engineer to say for sure. As for the VIA versus the WDC replacement... it's a data point, I'm not sure why one would work and not the other, but if you're able to swap them, that might be a good experiment.

I don't think so. As far as I'm aware, ghofbauer's change was just to switch the PIC's config to use an external clock source and divide it in half so it had the same instruction clock rate as the original. If you're seeing 1.6 MHz into the PIC, that should be it. I'm lacking context, what...

I've got nothing, I'm afraid. =/ To the best of my knowledge, the instruction clock is the only thing that should be different between the real thing and the PIC16F88/87 adaptation. If I had a better understanding of the code and the affected machine to test with and a whole load of free...

I haven't, actually... don't know my way around that source tree too well, but maybe will dig a little and see if I notice anything obvious. I no longer think it's realistic to do this in one 1504, I keep bumping my head against the macrocell limit. Going to try two like I originally...

My understanding of the IWM spec (and the Disk II) continues to evolve, albeit slowly. In the Disk II, Q3 (2 MHz, twice the clock frequency of the Apple II) is the only clock that exists, so it's used for everything. In the IWM, Q3 is only used for writing data in synchronous mode, FCLK (in...

Aha, you're right. Must be because Apple knew they'd be offering the FDHD upgrade. Maybe I can do some experimentation on my pre-FDHD SE...

Am realizing that it will be at least useful and at most necessary for me to get an actual IWM to test with... ideally a test machine with a ZIF socket where the IWM should be, too. Guessing I'll just have to keep my eyes peeled for someone selling a Plus or earlier in good condition (not sure...

I wish I understood better what the "latch mode" bit in the IWM was for. Apparently the latch mode bit "should" be set in async mode, but the spec sheet also says "In port operation, which is asynchronous mode true and latch mode false with /DEV held low indefinitely, read data will appear...