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Just saw this was already picked up. 

@quorten Looks like you've got quite a bit of stuff there. I've got a copy of VCS, so I'll get it up and running there. I owe Synopsys a SNUG paper for loaning it to me, so maybe this might end up there. I'll take a look and see what I can gather. I immediately focused on one of your points, in...

I can hop on a call. I'm not sure what I can add so far. I'm happy enough to throw in my experiences with capturing PCI traffic on a board I developed using my trusty albeit aging logic analyzer and what I could try to do with it to try to capture stuff in the ASIC. I'm happy to help...

Always. I think @maceffectswas making a breakout board. If I can get a hold of an SE with the breakout board I can ressurect my HP logic analyzer. I'm also open to other ideas on how to figure out what is going on.

I'll need to find someone good at soldering :)  I can't solder to save my life, but that looks like it would let me monitor what is going on, thanks.

@Kai RobinsonI lump CPLD and FPGA kind of together as their is much overlap in parts. I tend to like Xilinx as they are my daily driver at work, but certainly, whatever does the job. Schematics would be helpful. I have a 16550a logic analyzer I could hook up to the BBU if I could find a good...

Hi! I am hoping I might be able to help some in your reverse engineering/ re-implementation projects as well as get some help. I'm an FPGA designer with about 30 years of ASIC and FPGA experience. I've released my open source GPU: https://github.com/asicguy/gplgpu. I'm happy to provide my skills...