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Interesting. I'm relying on the logic board's ~CAS0 and ~CAS1 lines as input and assume that they are toggling as required since they work for the logic board's 512K of RAM. There must be a good reason to gate the ~CASF lines with C2M that I'm just not seeing. Taking another look at the...

Incredible! I'm really glad you're diving into the MacSnap so deeply. Looking at your snippets of schematic you put together in a previous reply, I also noticed that it seems like the '253 would latch depending on the state of its other inputs, and I was curious what the purpose would be. I'm...

I think this may only be necessary when trying to implement an amount of RAM which does not fully populate an address space such that the final address of RAM is NOT all ones following the highest address bits used for RAM selection. What I mean by that is to implement something like 1.5 MB of...

Thinking about the MacSnap a little more, I don’t think it generates RA9F at all as it can’t use it. It’s using the same size of DRAM IC as the logic board, so they have the same number of address pins for which RA8F is the most significant bit. That’s why instead it has to generate so many CAS...

Thanks for the pointers, Builder68! I tried a few other configurations, but ultimately the system only worked properly when only the on board RAM is enabled. Your advice is leading me to break this into smaller pieces and build up from there. One thing to note: because the system’s RAM is based...

Since I hadn’t taken apart the original breadboard circuit, I’d only disconnected it from the logic board, last night I hooked it back up. I did add AND gates to the CAS output lines as I drew on a schematic in a previous reply. This was to allow the pair CAS0F and CAS1F or the pair CAS2F and...

I think you’re exactly right. In the scenario you described when the logic board CAS is low, but the ‘139 output is high, a voltage divider is formed. To simplify, let’s say the system’s CAS output is perfectly 0 V, and let’s also say the high output of the ‘139 does not contribute to the...

Okay, I've got some evidence to back up my thinking. Indeed beginning with C2M high, an address would be placed onto the bus (thus to the '253s). With C2M high, the '253s present A1-A8 + A18 to DRAM which is latched in as a row address when ~RAS goes low. After ~20-35ns, C2M goes low which...

I guess this is too old to edit, but based on my thoughts from looking over the MacSnap board, I think it should read: I'll double check this when I can get back to my bench and probe the running system.

I like the way the MacSnap creates the CASF lines better than the approach I was taking. Using separate '139s for each CAS pair, rather than a single '138, and feeding them the same select signals allows one, the other, or both CASF lines for a pair to be asserted. C2M is ORed with the logic...

They are probably A17 and A18 to generate RA8F. On the Mac 512K, this is already done on the board at U13G, but the Mac 128K doesn't have this. The 128K->512K mod outlined here takes signals from RP1 to do so. You can see it here on the part labeled "512K only". The '253 is incorrectly...

I stumbled upon a version of this on Bitsavers. There are also some other GAL reversing stuff there as well. What you linked is very interesting! I like seeing handwritten notes and k-maps. Haha Looking at the Mac 128/512K logic board schematic, its apparent that the '253s that create the RAM...

It’s got to be a timing signal which is used to multiplex addresses for CAS and RAS.

That would make sense

Thank you for putting in the effort to trace this out! I’ll look into this soon and try to noodle out how it works. I’d like to know for sure what the Mac’s C2M signal does. A while ago, I thought maybe it was some recreation of the A0 signal which is not present on the 68000, but I don’t think...

This has got to be one major reason why my breadboard prototype didn’t work. I know I should just finalize the next schematic and lay out a PCB, but it’s very tempting to modify the breadboard circuit, reconnect it to the Mac, and see if it works…

My mind wandered back to this project while I was at work today, and I couldn't help but think about how the technique I'm borrowing from "Classic Mac Tech Docs v1.1" to generate additional ~CAS lines only allows for upper or lower byte of RAM to be accessed at one time. That didn't sit right...

I'm working on the schematic redraw, and I have an idea for connecting the ~OE pins on the DRAM ICs like the Mac Classic RAM expansion card without adding any new ICs. I'd like to hear opinions from others as the approach splits memory across the two DRAM ICs in a funny way. The Mac Classic...

Thanks! It can be a little meandering at time, but I find talking (or typing) my thoughts out loud helps me understand them better. Hopefully, it helps others too.

Agreed, that’s a great sign that it should work for this project! Thanks for sharing this. I saw a blurb in the schematic in the linked GitHub repository talking about using an AND gate to control the ~OE line to the RAM ICs based on either the upper or lower ~CAS lines being asserted rather...