Search results

I finally figured out and fixed the sound issue with the 512 cycle refresh mod! As suspected, VA8 and HIGH being swapped between RA0 and RA8 results in some sound data being stored (initiated by the CPU) into a new location in memory, while the sound hardware for accessing memory is still...

You could try adding some capacitors between +5V and GND near ICs on your prototype. Another thing could be any 74LS253s used on the prototype could be swapped with 74F253s dive that is what Apple used in the Mac. I believe the 74F series has a shorter propagation delay. That may not be the...

I socketed U2F, lifted pin 2, and pulled it high. Unfortunately the startup sound is still horribly distorted. Very interesting…

I have not, and I recall you mentioning this difference previously, and I never really thought too much about it. I hadn't realized it was part of the sound circuit, and I just now noticed that it produces RA# lines which didn't make sense at first until I noticed it's only active during DMA...

I played around with swapping those signals on U4F and U13G at first by cutting traces and wiring bodge wires, but decided to put together a couple little carrier boards which connect all the pins of the ICs back to the logic board except those which we want to try to swap. The pins to swap are...

Oh okay, I must have misinterpreted you. Very interesting info! Looking forward to the arrival of your DRAM and your experimentation. In reality, I won’t really have the time to play with my setup for a few weeks, but I might get the urge one night and lose a little sleep to try out the...

Almost. According to this, the Mac uses 21888 bytes of memory for video RAM. That must be for both the main and alternate screen buffers selected by the VIDPG2 signal. So for one buffer written to the screen, it’s 21888 / 2 = 10944 locations accessed at a rate of 60 Hz. Crunching the numbers, I...

Builder68: Rather than dedicated system down time for memory refresh, I assume that DRAM refresh on early Macs is accomplished by the video circuitry simply reading video data from RAM to draw to the CRT at ~60 Hz per entire screen draw. That's ~16 ms for the entire 14-bit video counter. Only...

Indeed, the video circuitry is providing the refresh functionality on the early Macs. I understand what you are saying regarding the connection of these video address lines creating the limitation of only 256 cycles for refresh on the Mac 128/512K, and the benefit the Mac Plus has in its video...

Just for fun: If one were to stick with the original size DRAM ICs of which the Mac 512K consists, it would take a whopping 64 ICs! But the 16 ICs onboard could be kept in service, so only an additional 48 is needed. I think something from my notes in my first post was close to correct for...

Did you mean to say most significant bit? The LSB would be RA0 corresponding to either A1 or A9 depending on C2M’s state. Or VA0 or VA8 if video is accessing memory. I don’t understand what the problem is? For the original 128K Mac, there were only eight RAM address lines. RA7 was the MSB which...

This seems like a possible approach with enough research and experimentation. Have you looked into hidden refresh? It looks like it’s pretty much the same as CAS before RAS except the data output remains valid on the DRAM outputs in hidden refresh. Not sure if that would be required or not.

I’ll dig into the Mac Plus schematics a little deeper later, but at a glance it looks like the Mac Plus does provide 9 varying row addresses which would be sufficient for a DRAM with 512 rows to refresh. The Mac 512K and 128K only provide 8 varying row addresses which only refreshes 256 rows...

Could probably get away with just two of these bad boys right herr. We could use just two 8 bit latches for RA0-RA7 and forget about RA8. The benefit would be that it could be compatible with 128K boards. Although It seems like people are more interested in restoring them back to 128K than...

That could be an option. No refresh necessary but requires nearly 20 address lines. The speed is probably just fine though. They may even be fast enough to allow for some prop delays through latches if we wanted to continue using the RA0F-RA8F (or even RA9F) lines and use latches to save their...

Damn. They're right, and it applies to the Mac 512K as well. The truth table I posted in this reply shows that during video access, the DRAM is given row address values from VA0-VA7 for ~RAS (C2M high). If the video circuit cycles through these addresses in a counter, and we can assume the...

I wouldn't say my design works quite yet. I took nearly the entire design out of the circuit. Haha I do think we should sprinkle in elements from the MacSnap design, but for now I'm still at the very beginning of trying to just get external 512K working.

I should note that at one point I thought that perhaps the RAM-R/~W line was being overburdened, so I clipped the leg on R33 which goes to the logic board’s RAM ICs and tapped it at that point instead. This left only my two buffers and the two 1 MB DRAM ICs as the only loads. It made little to...

I also tried the above configuration but with the RA9F generation in place to utilize the entire 2 MB of connected memory. This resulted in a decent looking screen during the power on tests, but it failed to complete them. The screen still has bad pixels here and there which indicate bad or...

I had some progress last night. I finally saw a happy Mac! Okay, well not a happy Mac but a Mac which passed power on tests and was awaiting a boot disk. It was very short lived. See the attached clip! This was a test of 512K memory, but expansion memory only. The logic board’s ~RASF, ~CAS0F...