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I'm still wary about this. In an unmodified Mac 512K, the only signal which isn't held high for RA8 while C2M is high (which is the state when RAS goes low, latching row addresses into DRAM) is the CPU accessing RAM via A18. There's no way the video or sound hardware can do it, so half of the...

Correct! That's why I mentioned RA9 generation: RA0-RA9 equates to 1MB on a DRAM IC, so only 4 banks and associated CAS lines required. It certainly seems to complicate things, and it tends to diverge from core elements of the MacSnap design in favor of leaning on elements of the Mac Plus...

Absolutely! :D

As far as I know, the ROMinator would only be selected when the system is accessing data in the ROM area of the address map, and RAM would not be selected. Same goes for vice-versa. The ICs are just not enabled unless their select logic allows them so. I'm not sure I understand what the issue...

I searched high and low for those type of connectors and came up short. The path I was thinking would be to desolder ICs and a resistor pack and replaced with sockets to which pin headers would mate, but only the standard 74 series logic stuff. No PALs to be desoldered. Then solder jumper leads...

This is fantastic news! Just to clarify, your expansion RAM requires 512 cycle refresh, but you are using the system’s unmodified RA0 and RA8 signals? I’m surprised it’s so stable! I’m glad the added input buffers seem to work okay; I suppose I probably didn’t need to order that Mac Plus logic...

Based on this table, the MacSnap ~CAS#F generation circuit reversed engineered by Builder68, and all the other stuff from this thread thus far, I've come up with the attached schematic for 1024 cycle refresh DRAM. It's untested, and there are probably mistakes. However, I wanted to transfer...

Edit 3: The last case (OEa LOW; OEb HIGH) is actually MCAS0, MCAS1 or MCAS4, MCAS5 depending on A20. MCAS6, MCAS7 would never be selected in this case. It's such a weird arrangement that there's no way this should be a valid case.

Edit 2: for the last case, the system may only recognize 512KB of memory? Only MCAS4, MCAS5 would be mirrored from 00000-FFFFF, and MCAS6,MCAS7 would only activate starting at 180000 since it is dependent solely on A20 with A19 having no bearing. It’s probably a “do not use” configuration.

For a minimal configuration, I believe pin 1 (OEa) and pin 15 (OEb) must both be pulled high. That would only ever select MCAS0 and MCAS1. This is what I worked out for all configuration options for that circuit (in terms of total memory including 512KB of logic board memory): OEa HIGH; OEb...

One other thought: try to get 74xxxxx components which match the exact type as the ones on the MacSnap board. By that I mean 74LSxxx, 74Fxxx, and 74HCTxxx. Each of these will have different propagation delays, and since there seem to be a mix of types on the MacSnap board depending on the...

This probably won’t change anything, but you could try connecting the unused inputs on the 7432 to ground or pull them high with pull up resistors. Someone reported to me that they did that once, and it actually fixed issues they had with a design I did to modify an arcade game. It worked fine...

I was looking at the Mac Plus schematic again, specifically at its bus transceivers ('LS245s). The pin used to switch the direction of the data bus to/from RAM is connected to RAMR/~WF. That's the same signal we are using to control the OE pin on the added input buffers. Interestingly, the OE...

Thanks for the tip and the link! Definitely a loose connection on bit 12 and sometimes also bit 10. For a moment IT WAS BOOTING! But then it crashed. Since then it’s just been 031000 and 035000. I’ve wiggled, cleaned, reinserted, and everything I could think of. It’s very motivating, and I’m...

There’s not necessarily a precise time for this to occur other than before 4ms has passed since the last time it occurred. It doesn’t really matter if it happens out of order with respect to refresh row addresses. They don’t really care about the other rows, so long as each row gets refreshed...

My understanding for the Mac’s refresh and DRAM ICs aligns with what you’ve stated. I’m probably going to sound incredibly redundant, but I’m typing this out for my own understanding! The system counts up through the rows of memory by reading data to display on the screen. RA0-RA7 (when C2M is...

I can get a nice clear boot screen now, just by reseating some ICs in the breadboard and trying to make sure each wire is fully inserted. No noise on the screen, great clear audio on startup, but still fails with a sad Mac. Not sure if my DRAM ICs aren’t happy with only 512 cycle refresh even...

I’m excited to read about the results of this mod on your 512 refresh cycle memory! By the way, I tried this 512 refresh cycle mod out on my 1024 refresh cycle memory with RA9 pulled high (also tried again with it pulled low, no change), and it didn’t worked. The audio sounds okay, but the...

I suspect this would work for 1024 refresh cycles, but this will need tested to know for sure:

Does that mean your prototype board is only receiving 256 cycle refresh? I would be surprised if that worked at all!