Search results

Excellent! Looking forward to seeing your results. In the mean time, I’ve been slowly wiring up a soldered prototype for using two AS4C1M16F5 ICs for 4MB (disabling system 512K). I received them as well as the DIP breakout boards last week. We’re both working off very similar designs at this...

Great work laying out these PCBs! One thing I spotted is pin 1 on the aux board’s ‘253 should be connected to DMA instead of ~DMA. I think the ~DMA signal is also accidentally connected to a signal used as a pull up for a bunch of other inputs. Other than that, it looks good to me! I haven’t...

I concur! Two smaller boards would be advantageous for all the reasons you mentioned. I’m excited to see how they turn out!

Are you saying you have a Dove SCSI add on board as well as a memory expansion? If so, do you think you can fit the ROMinator on top of the SCSI add on board (if the pins align with the IC sockets) to test that?

Mine is the SUPERMAC TECHNOLOGY SCSI board, and It uses Mac Plus ROMs. I think all SCSI upgrade boards for the early Macs use Plus ROMS? Someone successfully reverse engineered the MacSnap SCSI board: https://68kmla.org/bb/index.php?threads/reverse-engineering-the-macsnap-scsi.37901/

I wish the 5380 SCSI controller had a device ID register to read to check for it. I’m not sure it can be done in the same number of bytes, but maybe there’s a register in the SCSI controller to which we could write a value and then read it back to confirm that it’s really there. Hopefully...

Do we know if the ROMinator is still supported and if the author would be willing to investigate a fix? As an aside: If a Mac 512K with greater than 512K of memory also had a SCSI upgrade board in place, would the ROMinator work with it?

Did you mention in a previous reply that you did get the ROMinator to boot with the RAM expansion but only when it was configured to only provide 512K?

This also likely rules out the ROMinator preventing some type of fancy CPU-based scheme to aid in refreshing 512 cycle refresh DRAM since I’m pretty sure the DRAM on the MacSnap only requires 256 cycle refresh. We’ve come so far in our understanding, and I’d really like to get to the bottom of...

According to this: It doesn't really make sense that the ROMinator would try to access that address range, but perhaps there's some kind of issue regarding this?

I confirmed that a Mac 512K has *no issues* booting with a 2.2Kohm pull up resistor installed on A21!

Wow, I can’t believe there’s no pull up on A21 on the Mac Plus. I confirmed it on hardware; there’s greater than 4Mohms from A21 to VCC. That’s a strange one!

I’m pretty sure there won’t be any unintended consequences for adding a pull up resistor to A21, and it definitely will be required! Later today, I’ll put in a pull up resistor onto A21 on my board which is presently configured to be totally stock (except for the SCSI add on board with Plus...

Imagine using 128 256x1-bit DRAM ICs to build out 4MB! 😆 It would look something like this 4MB multibus card I have, except this card does parity checking, so it has 144 DRAM ICs.

Something like this:

This is so great! It seems super stable. So I know it’s wayyyy too many ICs, but hear me out. You could take that MacSnap design and add another ‘253 (only half of it need be implemented) and hook it up just like the existing one but with A21 as its input. Then replace the ‘139 with two ‘138s...

Interesting postulation! I wonder if there’s a decent emulator with breakpoints and the ability to view memory addresses and disassembly for the early Macs? It would be awesome to dive in deep to see if we can identify something like that happening.

I could burn some stock ROMs, but the EEPROMs I have on hand are either too small or too large. I could use the larger ones and make adapter sockets though!

My system has Mac Plus ROMs since it came with a contemporary SCSI upgrade board. I would be interested in having a copy of your prototype to probe and test! If you get around to laying out a PCB, I would definitely order one and associated parts. For the path (more like rabbit hole) I’m...

This is my understanding for refresh as well. The video circuit is counting sequentially for 256 rows via RA0-RA7. The video circuit can not toggle RA8, and it can only be accomplished by the CPU. The order doesn’t really matter so much as long as each row is refreshed every 4 ms. The CPU must...