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Well, the bits of the address-data-control bus need not be valid all at the same time. Here's a timing diagram for an address loading operation, where the 32 address bits are latched into the address glue FPGA: (this diagram strays from established conventions in some ways but whatever) The...

Well, the bus speed doesn't work like you're saying. There is the bit transition time, which can be specified in terms of the time it takes to rise from 10% to 90% or fall from 90% to 10% (of the logic level in question). That's what limits the GPIO pin performance to 40 MHz or so for...

Let me explain how I will structure the software. This should address the concerns you have raised, Gorgonops.   The emulator engine itself should be a chunk of C code with few, if any, external dependencies, in terms of libraries and the OS it must run on. Of course, the entire RAM and ROM of...

I tried to talk to the developer of the Apollo core. Originally, I wanted to license his core and synthesize it in a Cyclone III or IV FPGA. He never answered. I thought could maybe develop a 68k-compatible core and synthesize it in an FPGA, but I'm not really interested in that. So the...

Hmm but maybe some of the peripheral stuff isn't as free as I may have thought. For example, emulating the VIA and other members of the chipset is different from adding more I/O devices to a system which already has a physically working chipset. However, this work shouldn't be too terrible. The...

I wanna stress that I don't plan to implement grayscale video or video output myself, or any of the peripheral boards I've given rough designs for. (I may become frustrated and design the USB/JTAG header board while debugging the Maccelerator though. It's pretty easy.) I really am just trying to...

Yeah, the ideas for features are out of control at the moment. I don't plan to implement all of the features I've been planning for. I just think it would be a shame to sell this $150 thing and for it to be impossible to upgrade it to add some feature like video output. So I'm trying to strike a...

The other part of the bad news is that there are currently 120 components which must be placed on the board... Most of them cost between one and ten cents, so the problem is strictly assembly cost, not parts cost.

And another thought... the display sub-board connector is like $1.50 and will probably require the board to be bigger (maybe would cost another buck or so). Routing the DSI interface on the board is also a bit difficult (time-consuming and error-prone might be a better description) because it's...

Here's another nagging detail about the grayscale output on SE/30. Note the bandwidth requirement for 8-bit grayscale on a compact Mac. 512 x 342 x 60.15fps x 8bit = 84 Mbit/sec   84 Mbit/sec is very manageable over USB, so maybe the grayscale output should be a feature of the I/O board for...

Thank you for the encouraging words, sstaylor. I've abandoned the idea of using the processor itself to do the timing-intensive work for interfacing with the bus. Instead, I've implemented a design where 3 very cheap FPGAs implement the bus logic. The FPGAs are from Lattice's MachXO series and...

I finished fixing most of the problems in the schematic I mentioned yesterday, but now a new issue has come to my attention. Something like 46 pins are required to operate the 68000 bus and 53 are required for 68030. Plus there are 6 (4 and 2) signals for two UARTs. I am gonna more heavily...

In addition to the Variscite Dart SD410 module: http://www.variscite.com/products/system-on-module-som/cortex-a53-krait/dart-sd410-qualcomm-snapdragon-410 There are also these options...

I've made a lot of progress on the accelerator card schematic for the Mac SE. I'm attaching what I have so far as a PDF. I'll release the KiCAD .sch files when I feel it's finished. There are some problems, oversights, areas of sloppiness, etc. in the current schematic. Maccelerator-SE.pdf In...

Well, the Snapdragon 410 is quite fast compared to basically anything else at anywhere close of a price-point. I was stupid to try and get it on a board myself... the tooling costs alone would be $1200+, and then as much as $100 for each PCB. So the Variscite SD410 module seemed to be the...

I've been looking into how to convert the Snapdragon's MIPI-DSI display interface into something supported by modern monitors. Unfortunately, there does not seem to be an easy solution. Few ICs exist which convert DSI to anything useful, and the ones that do are usually very small BGA-type...

I have reworked my design. The major changes are: - Processor board (Snapdragon 410E) sourced externally, not designed by me - FPGA has been eliminated - No USB 3.0 - Has microSD slot on accelerator board - Small CPLD implements interrupt priority control   Here are the block diagram pictures...

TI AM437x may also be a good choice. Only $20 for a 1 GHz one with a Cortex-A9 and four PRU cores. I understand the Cortex-A9 in these chips to be a good bit faster than the Cortex-A8 in the AM335x series. There's also NXP's i.MX6 series, which goes down to around $30 for 2x ARM Cortex-A9 at...

The PRU-ICSS system in those TI chips is really cool though. I just figured that I could do the bus communication on the main processor, but the timing predictability of the PRU system is attractive. I figured the strategy of performing a bus access on the main ARM chip would be to poll the...

Well, the problem with those chips is that they're ARMv7-A. We could use them, but I have a preference for ARMv8-A since it has 31 general-purpose registers to ARMv7-A's 15. That's convenient because M68k has 16 registers, so on ARMv8-A, we can fit D0-D7, A0-A7, PC, status register stuff (X bit...