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@LaPorta Thank you, but there’s no need! I’m pretty sure this hardware is gonna work, and I’ve been sitting on boards and parts for a while. I’ve gotta make the driver, verify the sort of low-level hardware programming in the big chip, and then make the boards. Little additional expense is...

@Gorgonops Yes, there is a good reason to use SPI flash instead of an SD card. The goal was to make the fastest disk possible. If I want to move 16 bits off of an SD card, I need to have a clock going faster than the CPU transfer rate to serialize the data, plus more macrocells and...

I will proceed more quickly then since there is interest! Hopefully someone with some experience in driver development for the classic Mac OS can come along. I've read Inside Macintosh, but, unless I missed something, there isn't much about how to install a new driver in the system, though...

Hi 68kMLA, Maybe some people here remember my ARM-based "Maccelerator" proposal from a few years ago. I have cost-reduced the BOM for that project significantly and plan to get the hardware released soon, but that's not for today. Since the Maccelerator proposal, I have been working with a...

Yes!! Emphatically so. In the past year, I’ve been getting my home lab up and running, working on my other electronic product, and figuring out how to develop a US-based factory to assembly my circuit boards. I am still adamant about my direction of the project, emulating the 68k code on an ARM...

Yuhong! I have seen your comments on folklore.org. It is nice to see you here. I have been looking for some clarification on this subject for some time, but I still have a question. I understand these machines to dedicate a total of 1 Gbyte of the 32-bit physical address map to memory, between...

When the emulator is executing code on the virtual 68000 (i.e. doing the algorithm I described above), a special register usage convention will need to be maintained. Rather than the traditional ARMv7-M ABI, we will use our own convention for the emulator kernel. Certain important...

Yeah, I looked at it a few days ago. It's really impressive though its use in later Macs is maybe questionable since there are no plans for an MMU. I have to find out how System 6 and 7 use the MMU on 68030 systems to see exactly how detailed the MMU implementation has to be. Yeah, most of mine...

Now there will be a lot of branching and stalling the pipeline and branch misprediction and all that, but let me point out: The STM32H7, at peak, delivers 800 MIPS, compared to the Macintosh Plus, which delivers only 1 MIPS at most. Similarly, the STM32H7's SDRAM interface has a peak throughput...

Register-register operations have a straightforward implementation, but then there are instructions that perform some reading or writing of memory, actually most do this since it's CISC. There are also branch instructions which require a more complex implementation. Now when accessing memory...

Honestly, I have not studied Basilisk II at all, and Mini vMac only briefly. So I don't know how their 68000 emulation works, but I imagine it's similar to the scheme I have come up with, other than the fact that my design is to be run "on top" of a working Macintosh and its chipset. The entire...

Well the basic steps required to execute an instruction which has already been decoded are: Fetch the decoded instruction from the decoded instruction cache array. Take off the top 10 bits of the decode instruction and use that as an index to branch-and-link into the instruction...

Most 100 Mbit/sec Ethernet transceivers use the "Media-Independent Interface" (MII) or the "Reduced-pin-count Media-Independent Interface" (RMII) to talk to their host . Even the RMII interface has 10 signals to route. I'm running out of I/O pins on the STM32H7, so I was hoping to get a 10...

I am considering adding Ethernet to the design. Is 10 Mbit/sec sufficient, or should I go to 100 Mbit/sec?

Well, the Maccelerator is an accelerator in the sense that the purpose is to go into a Macintosh and make it run faster. On the other hand, it has neither a hard 680x0 or an FPGA capable of hosting a 680x0 core. Instead, 68000 instructions are executed under emulation on a fast (400 MHz...

Some more work on the power stuff on the SE board from yesterday and today: This image shows my progress on the internal power layer. The pink represents areas in the the internal power plane. The stuff on the right is 5 volts, and the snakey area under the FPGA is for its 1.2 volt core...

My friend (an adamant android fanboy), told me the same just now. I'll look into the prices. It's funny to mix technologies from different eras. Someone will one day find a Macintosh equipped with a "Maccelerator" and be totally confused. However, I thought I could get by with just the OTG...

The project has been coming along nicely. I annotated an image that shows my current progress: One new "performance feature" is that I've switched to two using SDRAMs. The routing for this is substantially harder than for a "point-to-point" system with just one SDRAM, but I can manage it. The...

Too expensive though. Those modules are $150 at least, and then the PDS board will still be fairly costly. I'd do the Snapdragon module before anything designed to carry a large, clumsy module like the Zynq-7020, and I'm sure I could get better performance from a JIT translating emulator running...

Commercial products basically can't involve out-of-spec operation of chips, so naturally nobody sold upgrades of this type. (Though some companies did seemingly certify 40 MHz 68030s to run at 50 MHz.) But for someone with some technican's skills, it wouldn't be too hard of a project, I don't...