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I learned from the linked post about the meaning of the parameters above: https://68kmla.org/bb/index.php?threads/wombat-650-800-board-overclocking-limitations.38538/page-11 #211 DCAS Pulse Width-Writes: If a 1, adds a clock cycle to the width of the second thru forth DCAS pulse of a write...

:D(y)(y)(y) Thank you so much.

How about RAM Chips? Is there a voltage regulator on the back side of the Module?

K4E640412D-JC50: 50ns, 4k Refresh 3,6V maximum Supply Voltage. https://www.datasheetcatalog.com/datasheets_pdf/K/4/E/6/K4E660412D.shtml No Voltage regulator visible on front side. So we learned: Even out of specification may work. Are the chips getting hot?

Are you able to share a photo of CPU prior mounting heatsink and a detailed photo of RAM module?

There are so many great information in this threat! But one thing I was not able to understand: What are the flags fastwr drpchg drpw cyc2ta dwcpw drcpw in djMEMC Configuration Register exactly doing? I already found; ROMspeed n add n waitstaits to ROM access mhz33 add one waitstait to RAM...

There are two other timings to change: RAM VRAM Which of the other parameters dwcpw fastwr mhz33 drcpw cyc2ta drpchg drpw affects what?

I played arround with MEMCConfig. Lowest 3 Bits are known as ROMspeed (As of Wombat description) LC475@25Mhz starts with MEMCConfig = $001A which is 0000000000011010 wich is ROMSpeed 2 I put my scope to OE of ROM and determined length of low puls: 120ns which is command (40ns) + 2 waitstates...

However, the LC475 uses its own config table with different values for 33Mhz and 40Mhz: 08049BC: MEMORYCTRLINITPATCH¹+$0156: $0101 ; 4*2 Byte Data MEMCConfig used for LC475/Q605 (and maybe other) $001A $00DC $02DC Some of the registers in which the table values are written are in a...

The LC475 ROM contains the tables listed below already known from the Wombat ROM. No bump configs found. 40804A20: MEMORYCTRLINITPATCH¹+$01BA: $0101 ; 4*2 Byte Data MEMCConfig used for Wombats $001A...

Next question to answer is: What is ROM doing in MEMORYINITPATCH based on the MachineID read from $5FFFFFFC? First read at $5FFFFFFC does not take care about the least significant bits, but do something for some specific machines. 40804872: MEMORYCTRLINITPATCH+$000C: LEA $5FFFFFFC,A2...

I was not able to read content of 0x5ffffffc with the debugger so I need to assume two things: Assumption 1: I can not read 0x5ffffffc because of MMU configuration. Assumption 2: The bit of Q605 Jumper and the two bits for clock speed are mapped into the lowest 4 bit of 0x5ffffffc. Assumption...

https://github.com/cy384/wombat-hacks/tree/main/rom-hacking helps a lot for disassembly and assembly of a ROM. Unfortunately the annotated-rom.S is out of a Wombat ROM that is different from a LC475 ROM and the annotated parts are about Wombat mostly. I found this article that gave me the first...

You are right, different board. It seems that neither your nor mine board does have prepared place for a antenna plug:(

External antenna at a raspberry pico W seems to be possible but not easy.

Is Wifi working with closed lid?

MC889xx need to be able to work with double CPU clock. MC88920 is specified up to 50Mhz, MC88916W70 up to 70Mhz and MC88916W80 up to 80Mhz. So for 40Mhz CPU clock an MC88916W80 is the appropriate choice. Others may or may not work. Maybe Brooklyn is able to tell what is needed to change this chip.

Am I right you changed MC88920 into MC88916?

Chips in the EBay offer are KM44V16104BK-5: 50ns, 4k Refresh 3,6V maximum Supply Voltage. No Voltage regulator visible on front side. The chips in your Macintosh are different but not readable from the photo (Samsung K4E6... I guess) Do you like to tell what chips you got? I am very interested...

Even if https://github.com/cy384/wombat-hacks/commit/9f1f30232b0881975be036df8caf0221606c534a#diff-b20f4edb8464831d8814e0bd4eca636594876ecbc1046116eec5c3214d6b1705 says "The Quadra 605 has a djMEMC derived memory controller and a lot of the information presented here is applicable to that...