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@demik I ordered some of @Kai Robinson 's PAL dump boards and I'll be assembling them soon. If you want me to send you one let me know. It seems like if that is the only thing stopping the project, that can be easily solved.
@demik wow! Very nice work, I’m impressed. Looks like you’re pretty much ready for prototyping. I don’t think clearance will be a problem because the MacSnap processor upgrade was taller IIRC. If you get this working and want to work together on making it a complete set, I can injection mold...
Yeah, I remembered seeing this somewhere else too, but I cannot recall the circumstances either. AppleNet seems like a sounds like a great project. It is probably a very niche one but still cool nonetheless. If I had more knowledge in that area, I'd volunteer to help.
It could be that or simply it was leftover parts. It’s really hard to say. I’d like for signs of having an Apple asset tag. For example, a spot where one was affixed would have less yellowing.
OK, yours definitely started life as a Mac XL and was never an upgraded. AppleNet never really happened. Here’s more info on that https://github.com/stepleton/applenet
What’s your Lisa’s Model Number? If it’s A6S0100 it started as a Lisa 1 and was upgraded. 1982 would be more in line with that. In the early days at Apple it was common to use parts available. If you had prototype connectors you used them so long as they were the same specs and production...
@quorten Sorry about my meandering mind. You see, I am not proficient in the skills to do much more than offer manual labor, funds, other knowledge, et cetera. Sometimes my passion and enthusiasm to pursue things gets in the way of reality. Anyway, I've been probing China to see if any chips...
@SlickClick interesting hypothesis. Certainly, outside of my domain but I would love to see a SE be able to get 12mb of memory especially coupled with 16mhz 68000 processor. I'll leave that to the experts, however.
I've actually found the 1.2a earlier version to be more reliable than the 1.8a PSU. I don't recall their common failure points but the 1.8a always had issues. In any case, this is a very useful thread for those looking to recap. Thanks @elemenoh!
I'm going to see what we can do without having to spend any cash now. I am really hoping to be able to clone the Brainstorm BBU rather than the stock BBU as it will be something we can learn from and be able to possibly make better than stock BBU without people needing the 16mhz PDS upgrade...
@ScutBoy thank you!
This appears to be SMD mounting. I think it can be converted to through hole DIPs. But I may keep it the same way. DIP and PLCC processors are available. @Kai Robinson I was initially worried that these were some kind of custom logic chip but appear too small for that...
@Kai Robinson they look lovely. Excuse my potential ignorance, but isn’t the SE limited to 1mb SIMMs? And if I recall many Macs of this era didn’t like 3 chip memory SIMMs. If you think we have a way to allow more memory, I’d be very keen on learning more.
Is there like a schematic out there with equations for any ASICs? If so, we can make quick work of that.
@fatal3rror yeah, sometimes they come up and cheap, its a patient man's game.
@asicsolutions has been working on an Xceed clone which includes video output for the SE/30 in color as well as internal grayscale. See this thread:
In the later pages some discussion was given. I should mention that this is a huge project and will take considerable time to complete.
@ScutBoy Seems like you had everyone worried it would be lost, ha! Thanks again for snatching that up. I really only need some high-res photos of the PCB. I really hope that it is through hole and without anything too advanced on the PDS card itself. If it is through hole, reverse...
@Unknown_K Seems like you have had bad experiences with FPGA. When properly implemented they can be better than earlier ASICs. That said, you are right about price. Due to limited quantities and often paired SoCs, the cost can be very high. Though with a larger market like the Apple II...
@quorten, thank you! This is some useful information. I think with the Verilog data combined with a logic probe, this shouldn't be much problem. Looks like you've done tons of work. Thanks for all your efforts.
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