Oh right. So I've just been looking up the PPC 740. It's a G3 with a PPC 603ev pinout no L2 cache bus and a higher potential clock rate. So, you replaced the old CPU (a 120MHz 603e)?
@cheesestraws , oh so it can have a compatible pinout, and still not work because it’s too big/small. I guess so, the 603e/117 in a PB5300c is bigger than the 603e/117 in a PB1400. (Though I should check).
@Snial - it doesn't look like they changed the CPU, it is visible in the second photo.
They probably have an L2 slot G3 upgrade. Sometimes the System struggles to tell between a 740 and a 750. But a 740 in place of a 603 isn't a huge speed boost. You get integer maths gains, but without the backside cache you just don't get the huge G3 gains clock for clock.
I briefly thought about it. For speeds in the 100MHz to 200MHz range I’d imagine that the 740’s missing L2 cache controller has less of an impact & the second ALU might bring it close to 604(e) performance?
I think I was imagining a 603e(v) Mac with an L2 cache, just not the backside one. e.g. you take a PM4400 with a 256kB cache and replace the 200MHz 603ev with a 200MHz 740 (or higher clock multiplier). Would it be faster than a 200MHz 8500? (Note, I don't plan to do this, I'm just pondering).
@Snial nah, without a specifically backside cache the performance of a G3 isn't much better than a 603ev. I'd expect the 604e to still out perform it in that scenario.
Although the internet tells me that the 740's branch prediction ability make it perform disproportionately well in reall world applications Vs benchmarks. But this might be disabled by default if the ROM doesn't know to turn it on for the chip type.
The big differences: the 603e has 16kB L1 caches; the 740 has 32kB L1 caches. The 740 has 2x ALUs, and dynamic branch prediction with Branch target cache. Both have 2x dispatch slots+BPU, so max IPC=3. Ironically therefore, since the LSU can complete out-of-order; 2nd ALU dispatch slots will get filled more often on load/store stalls & 2x successive ALU ops. Thus 603<<603e<604(e)<740<<750, surely?
Yes, so the 604e has quite a different architecture to the 740/750: 16kB L1 caches, 3x ALUs (1 dedicated multi-cycle mul/div), dynamic BPU+BTAC, 3x dispatch. In some respects like a 603e, but like a 740, it has multiple IUs. The similar BPU+BTAC and IUs & similar SPEC to the 740 imply they make a real difference (more code than we might expect needs 2x IUs/dynamic branches).
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