Recent content by trag

I think there are sometimes Muxes 74xx151, 153, or 157, most likely, that take data from the VRAM chips and route it in the appropriate number of color/grayscale bits to the DAC. The logic on the video card controls the Muxes so that the right data from teh right VRAM chip(s) are used in the...

Excellent sleuthing @Disappearing inc regarding the old documentation and such. The Outbound Laptop Model 125 has four extra SIMM sockets which, when populated, form a dedicated RAM Disk, with contents preserved by battery power when off (which makes the battery last about 24 hours when...

The machines had what was essentially a 6100 ROM set on board, according to one of the Daystar support dudes I communicated with, way back when in the days when if you called for support, you might end up talking to one of the engineers. These outfits were small. Often just a couple of guys...

Edited a bit since then... Sorry for not getting my thoughts complete the first time.

If it is outputting pure white, either 1) the IIcx boot process is not proceeding far enough to give you a mouse cursor and disk request icon,or 2) I would think that an input to the video card DAC is stuck high. That BT chip is the DAC. It should be getting data from the VRAM chips...

Excellent find. I remember the best upgrade for this era Mac once you got the Memory to 512KB or better is to add an external Floppy drive, to eliminate or at least vastly reduce disk swapping.

Not really a "consumer" level solution, but there's a resistor on PM9500/9600 which can be removed to disable the motherboard cache. Or maybe installed. R35? R31? Something like that. On the Umax S900/J700 board, there's a blank jumper position which can be populated to enable/disable...

My mind is back to thinking about caches. Playing ADD kid this week, I guess. I saw in another thread that you're building caches. Have you produced a PCB, or are you adding chips to existing boards with blank positions? I have a bunch of ISSI and Cypress chips that say Input pins...

Wish "like" was enabled over here. Then I could just click it to let you know I read and understood, when I have nothing further to add.

Interesting. Then while the first Bandit on ANS has six devices, there may only be five sets of PCI Request/Grant signal lines, because the Video controller does not use a set. One of these days I'll get out the multimeter and check, but if the CL-GD543X/'4X lacks any Request/Grant pins, then...

Correct. There is not built in ROM on the Beige G3. It's in the expansion slot, or not there at all. Later Note: Most of the following discussion is entirely from my point of view regarding what I am getting ready to design/build. Discussing what could be done in theory is a related...

It could be, but why would tying it low reduce the total amount of RAM that the machine will address? I could see it affecting performance, but capacity? Unless turning on bursts eats an address line, or something.

Thank you for the documents. I also wonder whether the ANS graphics controller has the ability to request mastery of the PCI bus. If it does not, then that is one fewer set of grant/request lines implied on Apple's PCI arbiter, taking it down to 5.

Is there some way to tell the host machine which of those two addresses to use? The problem, that I see, is that the host machine expects the ROM to be at a certain address, and when it is programming the ROM, it's going to use those same addresses. Or do you get to choose the address range...

Thank you. I see the CE_ connection now and it makes a kind of sense for there to be alternate resistors to RCS0 and RCS1, although looking at the G3 schematic, it kind of looks like they're using RCS1 for some kind of mutant OE/CE enabler on those two switches/buffers to drive some Data Bus...