Recent content by trag

Are you sure that wasn't the memory for the PEx? I can't remember what we finally figured out it needed. I think it was 3.3V though... And if that's EDO then presumably it isn't SDRAM, which is what the Beige G3 needs. The only memory I have in large quantities is the 32 MB 72 pin sticks...

Thank you for pointing out that thread. I missed that one too.

I'll take a look at those schematics. That is another route to the information that I want. Thankyou. It sounds like WE_ is just wired from chips to DIMM pin and then the chips rely on the motherboard to provide the proper WE_ level. But I did not want to assume that. It is entirely...

Deleted. Misunderstood post to which I was replying.

How the WE_ pins are wired. I know where they are on the chips and on the DIMM edge. Are the connected? Or do they run through some of those blank resistor positions on the board? Are the chip WE_ tied high? If so, how high (with what resistance)? The chips must be held high during...

Actually, all three of them, X100, X500/X600 and Beige G3 use the same pinout. I have some slight doubt about the X100 because I haven't toned it out with an ohmmeter, but IIRC, there's a pinout in the Hardware Developer Note for the X100 cache slot, which is interchangeable with the ROM slot...

Now on to the real reason I hunted down this thread. I bought one of these in late 2024. I can't find the darned thing. Can I please get someone to check the resistance between... Never mind. Typing that out seems to have triggered a memory. Found the thing on top of my Beige G3. Duh...

Necroing this thread a bit. When you folks were combining the chip contents into a full ROM dump, did you swap every pair of bytes? The chips are 16 bits (2 bytes wide). A ROM dump from the machine interleaves the four chips, taking two bytes at a time from each chip, but..... the ROM dump...

Thanks for linking me in jt.

JT's PEx booting https://68kmla.org/bb/threads/pex-rom-project.23568/post-417205 BTW, thank you for linking to that ANS thread. I have completely missed seeing that this year. I can build ROM modules for the ANS, but they are one-shot, not reprogrammable. In the (enormous) thread above I...

The ANS has two 53C825 Fast & Wide SCSI chips on the motherboard. They occupy two of the PCI addresses. It can also use PCI SCSI cards, of course, although which might have drivers would be interesting. I think there's also some kind of RAID card based on an IBM build available.

For some reason I didn't get the notification until today. But it looks like it's been covered, and while I appreciate the faith in my abilities, I don't actually know how to convert TTL to VGA. :-)

I don't know. But we ought to be able to figure it out from the schematic. I don't have the attention to look right now. On the X500/X600, there is clearly an independent 33.33MHz oscillator that drives the PCI bus. Every PCI slot receives a PCI clock signal, so I would trace back from...

If you're discussing VRAM on the built-in 6500 video, I suggested a way to neatly take it to 4 MB, here: https://68kmla.org/bb/index.php?threads/schematics-for-power-mac-7600.46119/post-545005 I have not tried it, but the 6500 schematic suggests that one could simply remove the old GRAM chips...

The PowerSurge family (X500/X600) machines have 3 pins on the CPU cards which serve a similar purpose. The Bus clock chip is always on the CPU card, so the resistors that tell Hammerhead what Bus Speed to expect are also on the CPU card. The pins are CLKID[0 - 2] (pins 15 - 17 on the...