Recent content by Melkhior

Upstream doesn't (yet that I found - I'm not even sure if upstream is maintained formally?), but there's a ton of AI-assisted work to add MMU and even FPU (which is a bit redundant as a FPU already exists as I linked... not going to complain about choice :-) )

As a post-68000 Mac & workstation guy, I *don't* want cycle accurate (when it comes to instruction timings). Cycle accurate is great for platform with timings-dependent software, like 8/16-bits systems & arcades, but it's not required for machines with more abstracted software layers. Also it...

Nice. AI seems to be helping push the hobby further - though the implementation you use (I think this one) is targeting functional implementation, and does not implement a clean MC68030 bus unfortunately (... as I wondered if I could use it as a core in the IIsiA7 Mini to replace the onboard...

Thanks!

Well, if his project needs an Intel i82586 or an AMD AM7990 (for Ethernet), tell him to ping me if he needs a beta tester :)

And it looks great; in particular having the option of multiple clocks. The Suska implementation is purely pclk-based, and while it does work for me in the Sun-2/Sun-3, it does require some specific relationship between the CPU clock and the baud rate, as in the original hardware - which is a...

Pictures lie :-) Quoting the GitHub readme: The implementation is here.

Do you have a reference for the Z8530 implementation? I know of a VHDL one in the Suska project (which I've successfully used to emulate the SCC used in a Sun-3), but it's interesting to have an alternate implementation, in particular in Verilog. But I can't find the original and the file itself...

Good, but trust is gone. Vivado in its free version "calls home". Nothing stopping them from waiting for the use of 2025.2.1 to drop and most people to move into newer yearly licensed versions, and then remove some of the free options... I suspect for many hobbyists (including me), trust is...

As said already, "Field-Programmable Gate Array". With more details... "Gate Array" are an old technology (early 80s) to create chip "on the cheap". A manufacturer (such as VLSI Technology) would put a bunch of sets of transistors ("gate") in a grid on silicon with some predefined pins for...

I think the Gowin stuff is somewhat supported by open-source tools, yes. The current issue is that the FOSS tools are not at the level of the incumbent's proprietary solutions that have been in the work for decades. So for really small FPGA it's OK, but the bigger the FPGA, the bigger the gap...

I'd recommend a real connector, preferably some sort of modern high-speed high-density connector. It helps with signal integrity issue and with mechanical support. Look at what is available in large quantity at JLCPCB, and that should be popular enough to be somewhat future-proof. (edit: i will...

Oh, OK, did not know that, I thought Apple had standardized the Quadra PDS for all Quadras (that have one, so not e.g; the 840AV).

The linux 2025.2 might remain usable (though it calls home, so you never now...), and the 2026.1 on Windows still has a free license though for one year only. So it's not entirely dead. I'm not sure what you mean; you want to plug a card-edge in the PDS slot ?

Yes, it's very short-sighted. Having really great support for your FPGA freely accessible to those who won't/can't pay is a great way to lock-in mindshare and expertise. Hobbyists, students, small companies were using those licenses. Without them, people are going to look at alternatives...