Recent content by mdeverhart

Glad you found it! I hope the rest of your build goes smoothly, looks like you’re on your way!

I’m afraid I don’t know, but I have one that needs to be recelled too and I’ll be eagerly watching the feedback here and your results if you attempt it!

I have a PRD-250 Discman and PowerBook SCSI cable, I'll try to tone it out sometime this week and will update the thread.

No problem, makes sense to me. I can't help with the toolchain problems (no experience with any of the Atmel tools, yosys, or the POF2JED flow, though I do have some Quartus experience), but I can potentially help with Verilog or VHDL questions and issues. Happy to help if there's anything I can...

Can you post the code for the clock generator? I’m happy to look on GitHub too if you want to post the code there.

Instead of handling the tri-state in each module, try only handling it at the top level right before the chip IO. Each module will have a data_in, data_out, and oe port which you can use at the top level. If the part actually supports internal tri-states then this will be less efficient than...

Can you post a small code snippet somewhere? Is the tristate/bidir code constrained to the very edge of the design at the IOs?

Awesome! I might have stumbled on that earlier when I was looking at one of your other projects, but I’d forgotten it. Thanks!

If you’re seeing sharp pulses that line up with the edges of adjacent signals - yep, that’s the problem. It would be a great service to the community if you could write up what you’ve learned, maybe as an addendum to the Apple IWM document that clarifies, corrects, and adds more detail where...

It’s been recapped - the original solder would have been much cleaner than that. They also replaced the cap at C36 (top of your picture) with a tantalum instead of the original electrolytic can.

That’s actually how Apple’s service documentation recommended doing it, so that the dangling leg could be moved over and resoldered if the memory configuration ever needed to be changed back.

Thanks. I knew they were bad about that, but I hadn’t considered grabbing a copy for this purpose, and I hadn’t looked into the MAX7000 support. Time to grab it and throw it onto my NAS. From the Service Source it looks like it’s a socketed DIP right next to the socketed DIP ROMs.

Congrats! Verilog is definitely a good tool to have in the toolbox. Good to know! I haven’t done any CPLD designs for Classic Mac hacking, but I’d been considering taking that approach since it’s about the only 5V CPLD available in production anymore.

Out of curiosity, what SCSI IDs are you using for images on your ZuluSCSI? Just one image of ID=0, or are there other images present?

I doubt you’ve fried the LB. There’s a lot that needs to work right in order to get to the point where it shows the blinking question mark floppy, so that’s a really good sign. A few guesses: 1. The floppy probably has a short somewhere, likely introduced when you recapped it. A short on the...