Recent content by DBJ314

PowerPC instructions always have 4-byte alignment. When told to jump or return from an exception, the CPU always ignores the low 2 bits of the instruction address and pretends that they are 0. No exception will happen, the CPU will just fail to notice the address was unaligned. PowerPC CPUs...

Capacitance and inductance (attempt to) tell you what properties the component will have at every frequency. Those quotes were taken from this blog post: https://lcamtuf.substack.com/p/primer-core-concepts-in-electronic. I found it a few days ago, and before that I had no idea there was more...

SheepShaver patches the ROM in quite a few places. Maybe some of them are convenient. https://github.com/cebix/macemu/blob/master/SheepShaver/src/rom_patches.cpp https://github.com/cebix/macemu/blob/master/SheepShaver/src/rsrc_patches.cpp

Source code for PPC exists. https://github.com/elliotnunn/supermario/tree/master/base/SuperMarioProj.1994-02-09/OS/PPC Any header files included would be here. https://github.com/elliotnunn/supermario/tree/master/base/SuperMarioProj.1994-02-09/Internal/C The Apple Event Manager source also...

If you are going to use two serial ports, you might as well use both of them for data and get double the speed. And then use the HSKo and GPi pins (HSKi would be used for the external clock) to bit-bang an extra bit of data per time period, to slightly increase the data rate even more. Crank the...

If you put a Driver Descriptor Map at the start of the GPT-formatted disk right where the boot block would be, the ROM will use it to try and load a 68k driver. The ROM will do so even if it doesn't understand the rest of the disk. That driver can then set NVRAM and reboot to make OF load code...

You could of course directly alter the process OF uses to probe PCI cards. The PCI probe process usually happens after the NVRAM script is loaded. It's just that line at the front of your script that does the loading right then and there. All the code and data in Open Firmware is in ram and can...

Those numbers are indeed IDSEL. The PCI Bus Binding to Open Firmware says so. The IDSEL is also the "Device Number" field of each entry in the "reg" and "assigned-addresses" properties.

I did it by reading the reverse-engineered source code of the NanoKernel. https://github.com/elliotnunn/NanoKernel The NanoKernel has a very complicated system to handle paging-related exceptions. A DSI Exception happens. (An Alignment Exception also triggers this code path). The faulting...

On PowerPC Macs, this code will designate a page as "Quiet Read-Only". Writes to that page will be silently ignored, instead of generating an exception. It can cause all sorts of interesting crashes and misbehavior. Most code assumes that when you make a memory write, memory actually gets...

The easy way to use discontiguous RAM is to have the MultiFinder/Process Manager put different Application Heaps in different RAM blocks. Applications don't care about where their heap is, so it's nice and simple. The hard way is to allow a single Application Heap to exist in several RAM blocks...

It probably sticks the RAM anywhere in the address space it fits, without worrying about keeping it together. The Virtual Memory Manager does this when in 24-bit mode to fit as much RAM as possible in a limited address space. The accelerator might use a similar trick. Here's page 3-7 of Inside...