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K Trueno

Daystar Universal PowerCache P33 in SE/30

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1 hour ago, K Trueno said:

@ktkm Here is a pic of my "jumper" :-D  Yeah its a paperclip right now.  I'll take more pics when I do it right this weekend, but there are markings on the PCB to for you to count (C is top row, there is 10 under the tenth pin, then  count over connect).   

Well done @K Trueno @Bolle and @JDW! I’m gonna try it with my TwinSpark tonight! This is the best thing that has happened this year!:)

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10 hours ago, Bolle said:

Pretty sure there is an address decoder on the PowerCache itself that takes care of only caching things that should be cached.

That would make sense and those (or that) Daystar engineers were pretty good.   Is there some mechanism by which the cache can tell whether the SE/30 is in 24 bit mode and the cacheable space is even smaller?   Or are the hardware addresses to memory always the first GB, and the memory maps documented are logical addressing rather than actual hardware addresses.

 

10 hours ago, Bolle said:

The external enable signal does not exist on the socketed PowerCache which uses the same GAL set. 

That is interesting to know.   How have you confirmed that the GAL set is the same? 

 

11 hours ago, Bolle said:

 

@trag the IIci is special as the memory controller in there can control an external cache. No other machine besides the IIsi has that capability. On the IIsi it needs external decoding logic that’s done by the GAL on the Daystar adapter.

 

If you take a close look at the SE/30 adapter that GAL is wired up different than on the IIsi adapter. Pin 19 of the GAL connects to /CENABLE. It is set to be low all the time in the fusemap. On the IIsi adapter /CENABLE connects to Pin 18 on that GAL which is only active if the memory controller in the IIsi wants to address an external cache.

 

Thank you for the information.  Interesting, as always.  

 

The memory controller on the IIci has some limited cache support/control ability, but I don't think it fully controls a cache, as all the caches I've seen for the IIci include some kind of programmable logic (or a big ASIC) which is probably handling BERR and such.   Caches for the NuBus PowerMacs, on the other hand, seem to consist of just a TAG RAM and a regular SRAM (in the needed widths), suggesting that either the NuBus PM memory controller or the PPC601 has cache control logic actually on board.

 

The PCI Power Macs just seem to have two sets of distinct SRAM, neither of them TAG, suggesting that the comparators have been moved to either the PPC or the memory controller.

 

However, take the above with a grain of salt.   That's my preliminary conclusions for a fairly rushed overview.   I don't know when I'll ever actually trace connections.

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You are right... „Control“ may be a bit much. Let’s say the controller knows that there might be cache. The external cache will be able to tell the main memory controller that there was a cache hit so the cache logic doesn’t has to race the standard memory cycles and abort them in between.

 

Don‘t have the original Daystar adapter so I couldn’t verify the contents of the GAL on there.

However all inputs to the GALs that I could trace from pictures of the adapter are the same inputs as on the IIsi adapter. Most of the outputs I could see do also match (other than the few differences stated above)

That made me think it might be the same.

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2 hours ago, Bolle said:

Don‘t have the original Daystar adapter so I couldn’t verify the contents of the GAL on there.

However all inputs to the GALs that I could trace from pictures of the adapter are the same inputs as on the IIsi adapter. Most of the outputs I could see do also match (other than the few differences stated above)

That made me think it might be the same.

 

I was referring to the PowerCache/030 vs. the SE/30 Socketed upgrade.   I may have misinterpreted, but I took this, " on the socketed PowerCache which uses the same GAL set. " to mean that you had determined that the PowerCache030 with the EuroDIN connector uses the same GAL set as the SE/30 upgrades which plug into the 68000 socket.

 

Were you perhaps comparing the IIsi/SE/30 adapter(s) to the IIcx adapter in that phrase?   Sorry for the misunderstanding.

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Awesome stuff going on here. I start to wonder why no one noticed this before.

Like nobody ever had the actual cache on the universal PowerCache working in an SE/30 before I guess (at least without the official adapter)

1 hour ago, ktkm said:

I’m gonna celebrate with a cold Czech lager!!! 

Cheers.

IMG_9217.jpg.fe8b848f912f07e01926cfd952a6bf34.jpg

 

And thanks for the kind words earlier today ;)

It's not like I totally know what I am doing, just can't stop digging around once I started.

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21 hours ago, Bolle said:

I start to wonder why no one noticed this before.

Like nobody ever had the actual cache on the universal PowerCache working in an SE/30 before I guess (at least without the official adapter)

Just a random dude wanting that last 3-4 MIPS out of a 68030 machine along with someone that actually knows what's going on! :-)

 

But yeah I think this is pretty big news for llsi Adaptor/TwinSpark/ProtoCache users.  I mean there have been these types of builds described on Gamba's site that would have the same problem.  Not everyday you discover something new 20 some years odd on, all thanks to @Bolle .

 

Don't have a pic, but, cheers!! 

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