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K Trueno

Daystar Universal PowerCache P33 in SE/30

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Thanks @JDW!  I ran some new benches, and this is what I see.  It really does seem my setup is really under performing yours!

 

Now I am wondering is it just me or other Universal PowerCache + TwinSpark users?

 

Mine-Universal-PowerCache-On-vs-JDW-Socketed-PowerCache-Off

 

Mine-PC-On-vs-JDW-PC-Off.png.f1788672d33a1fad9d6b9705a7facacb.png

 

Mine-Universal-PowerCache-On-vs-JDW-Socketed-PowerCache-On

 

Mine-PC-On-vs-JDW-PC-On.png.246febbada3d4f074905bd3197c1b469.png

Mine-PC-On-vs-JDW-PC-Off

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8.83 isn't too much under 9.4, but it's clear that because you get the same exact scores regardless of the Control Panel setting that something is wrong in the hardware, with that card and adapter combo not being compatible with the SE/30.  Being "not compatible" doesn't mean it won't work, but it's clear the performance gain isn't there, although you would get a gain over the stock SE/30 configuration.

 

The problem I am having is with lockups.  While running those benchmarks for you, I actually had more than one lockup.  It seems to occur as the system heats up, and this socketed accelerator really heats up, let me tell you.  (It can't be the analog board or PSU or motherboard capacitors, because all 3 are recapped.)

 

Have you contacted Manabu Sakai of ARTMIX to ask about compatibility with his TS Adapter and your card?  If not, please ask him.  His English isn't perfect, but he can surely understand that question.  Just be sure to state which TS adapter version you have so he isn't confused about that.  Use simple English sentences and you should get a reasonably good response from him.

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1 hour ago, JDW said:

 

8.83 isn't too much under 9.4

 

Right, so it’s as if the PowerCache setting has no effect and is off in my setup no matter what.  It is way under your 13.5 which is what I would expect!

 

1 hour ago, JDW said:

Have you contacted Manabu Sakai of ARTMIX to ask about compatibility with his TS Adapter and your card?

I plan to do so now with these benchmarks in hand, I wanted to rule out that I had wrong or misleading benchmarks.  I am sure I have loaded the Control Panel right through my PowerMath flipping, and also tested OS 7.5 through a boot floppy, so I am reasonably confident there is a gap.  

 

I still do do wonder what other folks with a Universal PowerCache + Adaptor are getting.  I also wonder if @trag benched his cacheless 50mhz Accelerator he won a few weeks back :-) 

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I have a theory... The Artmix adapter is a clone of the adapter that was made for the DiiMo Cache 030.

It looks like that one handles the /STERM signal different than the PowerCache. I will modify one of my adapters and see if the performance rating changes if I run /STERM through the GAL just like on the Artmix adapter or wire it up straight through between the PDS and cache slot on the adapter like Daystar did on the IIsi adapter.

Not sure how they did on their official SE/30 PowerCache adapter as I do not have one of those.

If the performance rating changes you can run a simple wire (or change the code in the GAL)

 

On the SE/30 DiiMo they are doing this in one of the GALs and I am pretty certain the same is going on in the Artmix/DiiMo SE/30 adapter as well. (at least I did this in my SE/30 adapter and I am getting the same results so I again I am sure this is what Artmix and I am doing)

 

CPUCLK=1 /STERM.PDS=2 GND=10 /nc11=11 o12=12 f13=13 f14=14 f15=15 CPUCLK.OUT1=16 
CPUCLK.OUT2=17 STERM.OUT=18 o19=19 VCC=20 

@ues 0000000000000000
@ptd unused

equations

o19 = gnd
o19.oe = gnd

/STERM.OUT = /f13
o18.oe = vcc

/f15 = /STERM.PDS * /f15
    + /STERM.PDS * /CPUCLK
f15.oe = vcc

/f14 = /f15
f14.oe = vcc

/f13 = /f14
f13.oe = vcc

/CPUCLK.OUT2 = /CPUCLK
CPUCLK.OUT2.oe = vcc
/CPUCLK.OUT1 = /CPUCLK
CPUCLK.OUT1.oe = vcc

 

If I get this right this will align /STERM to the 16MHz clock on the PDS interface and then delay it for a few nanoseconds (depending on the propagation delay of the GAL that's used) and finally output that signal to the accelerator.

I can imagine this might throw off the bus/cache logic on the PowerCache if it wasn't designed to wait for that delay.

 

 

In the end the SE/30 could be something totally special and require even more magic on the adapter to use the Universal PowerCache to its full potential.

 

 

EDIT: changing /STERM to straight through wiring like on the IIsi adapter doesn't do anything to the performance rating. :/

 

Edited by Bolle

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That's really weird... I will see how the Speedometer rating behaves when using the P33 PowerCache in a IIsi, II and LC (and I figured it's going to be ok in the IIci/IIvx as those have the correct slots right away)

Both of my PowerCaches are behaving the same in the SE/30, so it's not an issue with them. Someone with the original Daystar adapter would be helpful here now.

 

Edited by Bolle

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Ok, so on all other Macs the cache switch in the control panel does something and the changes get reflected in the Speedometer benchmark as well.

 

Cache works fine in the Mac II using the original Daystar adapter.

Cache works fine in the Mac LC and CC using the original Daystar adapter.

Cache works fine in the IIsi using one of my Topper adapters in Daystar configuration (which matches the original Daystar IIsi adapter)

 

Cache does not work however in the SE/30 using neither the DiiMo/Artmix nor the Daystar IIsi configuration of my adapter.

 

The only difference between the IIsi adapter and the original SE/30 adapter is a 74ACT86 that does some kind of clock buffering... at least the C16M and CPUCLK line from the PDS get jiggled around that IC.

I am not sure if our issue here is is related to the 16MHz clock signal going to the PowerCache though.

On the PowerCache itself the CPU clock signal from the host PDS is only used in one single location @GAL U14 so I don't see exactly why buffering should be necessary. :huh:

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3 hours ago, Bolle said:

Cache does not work however in the SE/30 using neither the DiiMo/Artmix nor the Daystar IIsi configuration of my adapter.

Wow @Bolle thanks for looking into it and reproducing!  Kinda glad I am not the only one! ;-) 

 

Hardware is over my head, but if its switchable in software then something must sense an address/instruction/data to "flip a bit".  It also seems that PowerDemo is able to "read/sense that bit" - does that stay correct in the Macs where the cache is enabled?

 

I mean, it could also be the Control Panel setting different addresses expecting a different adaptor in an SE/30 - maybe because of Slot $E being used for Video unlike the other Machines?

 

A quote from a certain "jt" gentlemen from a thread on thinkclassic.org.  I don't claim to understand much of it.

Quote

I think I may have figured out the source of confusion. In GttMFH2e, pp.389-392 list the signals available on the IIci cache slot. The bolded entries are signals Apple placed on the connector for diagnostics purposes only and would be the jumping off point for those "determined to design an expansion card other than a cache memory card," such as the PowerCache accelerators.

My theory is that something about Daystar's implementation using machine level interrupts /IPL0-IPL2 or some other "extraneous" signals available for operations "other than cache" puts a hurt on the function of cards at location $E that are not designed to operate within the framework of the Slot Manager operations. The video subsystem of the SE/30 may appear to occupy $E to Sot Manager, but there was no reason for Apple to operate within its own Slot Manager design guidelines for a "card" in a slot location in the SE/30 that's unimplemented in hardware. 

My theory is that operations of the PowerCache accelerator interfere only with those operations of slot $E that fall outside standard Slot Manager Design guidelines. Slot $E would therefore be fully functional in six slot Macs and the LCIII PDS that fall within those standard Slot Manager operations . . .

...but well and truly bork the SE/30's video subsystem, hence, the CPLD adaptation?

 

Also, there is an adaptor on eBay right now with some decent pictures, it gives a good view of the 74ACT86 and you can _almost_ make out traces in one of the layers.  I'll try to clean it up and put it up here and hopefully that can help.

 

Edited by K Trueno

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Ok... the one place the CPU CLK from the SE/30 PDS is going on the PowerCache is to GAL U14 as I said before.

That GAL seems to do some kind of clock distribution for that clock signal. It also connects to the "unused" pins on the cache connector.

It looks like they use those pins to determine the kind of adapter/machine the PC is plugged into and adjust the clocks accordingly (i.e. shift them in phase a little bit using the internal feedbacks of the GAL in some "unused pin" configurations)

There is an external feedback network hooked up as well using two caps but those two caps are not soldered into place on the PowerCache.

 

This is what U14 looks like in the schematics:

 

1965911374_Bildschirmfoto2019-06-12um14_36_32.thumb.png.a470c176d69272afb595648ea235d296.png

 

 

;$GALMODE MEDIUM

chip U14_1 GAL16V8

nc1=1 i2=2 i3=3 i4=4 i7=7 GND=10 /nc11=11 o12=12 o13=13 f14=14 
f15=15 f16=16 f17=17 o18=18 o19=19 VCC=20 

@ues 0000000000000000
@ptd unused

equations

/o19 = /i2 * /i4
    + /i2 * i3 * /i7
    + /i2 * /i3 * i7
    + /i3 * /i7 * /f14
    + i3 * i7 * /f14
o19.oe = vcc
/o18 = /i4
o18.oe = vcc
/f17 = i2
f17.oe = vcc
/f16 = f17
f16.oe = vcc
/f15 = f16
f15.oe = vcc
/f14 = /i3 * /f15 * /i7
    + i3 * f16 * i7
f14.oe = vcc
/o13 = /i2 * /i4
    + /i2 * i3 * /i7
    + /i2 * /i3 * i7
    + /i3 * /i7 * /f14
    + i3 * i7 * /f14
o13.oe = vcc
/o12 = i2 * /i4
    + i2 * i3 * /i7
    + i2 * /i3 * i7
    + /i3 * /i7 * f14
    + i3 * i7 * f14
o12.oe = vcc

 

 

Not sure if this leads us somewhere but it's the only thing I could imagine that keeps the cache portion from working correctly in the SE/30 because why would they have used the 74ACT86 on the official adapter to do weird stuff to the 16MHz clock if the clock wasn't important.

The "unused" pins (lets call them machine sense pins) could be connected to ground/vcc in a different manner on the SE/30 adapter as well.

 

Edited by Bolle

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Ok, way easier than all that:

Connect /CENABLE (pin C13 on the PowerCache slot on the TwinSpark) to ground and the cache will work in the SE/30.

Spotted that little difference from the IIsi adapter while looking at pics of the SE/30 adapter. :rolleyes:

 

Not sure if there is a jumper or something like that on the TwinSpark that will let you do this conveniently.

I just soldered in a patch wire on one of my adapters and I am now getting a score around 11.5 with my 40MHz P33.

I also noticed that the score gets changed a little bit when changing configuration of the "machine sense pins"

The external cache setting in the PowerDemo now also reflects the setting in the control panel and turning it on and off has an effect on how fast the shiny stars are redrawn :tongue:

 

 

Edited by Bolle

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1 hour ago, Bolle said:

Connect /CENABLE (pin C13 on the PowerCache slot on the TwinSpark) to ground and the cache will work in the SE/30.

1 hour ago, Bolle said:

Spotted that little difference from the IIsi adapter while looking at pics of the SE/30 adapter.

Good eye!  I was just half way drawing lines in those pics and it was rough with the lines in the layers.  

 

Can't wait to try to run a wire, after confirming here first if I got it right first of course :-)  

 

1 hour ago, Bolle said:

The external cache setting in the PowerDemo now also reflects the setting in the control panel and turning it on and off has an effect on how fast the shiny stars are redrawn :tongue:

 

Yay for fast stars!!! :-D :-D 

Edited by K Trueno

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39 minutes ago, ktkm said:

TS2.jpg

 

It doesn't look like C13 (I'm guessing that's 13th pin hole on the 3rd row has traces down near the jumpers), so probably not that?

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1 hour ago, ktkm said:

No C13 as far as I can tell. The top layer doesn't seem to touch the jumpers?

Nope doesn't seem so (but not home yet to check).

 

 

How about this way: can I run a wire in the connection hole or outside to connect C13 to GND (say, two holes up to C11) and try?

 

slot-layout.thumb.png.6586de2dd916e77c169ee03063600229.png

 

Edited by K Trueno

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Hmmm.  I was reading something, somewhere -- maybe in TGTTMFH -- the other day about the IIci external cache.  IIRC, it said that Cache Enable is only active for memory accessess.    So, the first GB of address space?   It makes sense, as you don't want to cache IO operations.   You can't count on I/O data remaining unchanged at a given address.

 

Anyway, it seems like tying it low so that it is always enabled could cause problems.   Unless I am misremembering which signal it was and there's some other "cache this if you can" signal.

 

I wish I could remember it better, but I was on a binge of cache information reading.   Kind of a feasibility study for adding an external cache to that pass-through upgrade I picked up for the SE/30 a few weeks ago.

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Hm, if that’s the case you will never get proper operation of the PowerCache in the TwinSpark adapter.

 

Pretty sure there is an address decoder on the PowerCache itself that takes care of only caching things that should be cached. The external enable signal does not exist on the socketed PowerCache which uses the same GAL set.

The Daystar Mac II adapter for example also just ties /CENABLE to ground without any extra logic that decodes memory addresses.

 

 

@K Trueno a small jumper from C13 to C11 will do. Just make sure before that C13 isn’t connected anywhere else (it shouldn’t connect anywhere according to my info on the TwinSpark but I don’t have one myself to check)

 

@trag the IIci is special as the memory controller in there can control an external cache. No other machine besides the IIsi has that capability. On the IIsi it needs external decoding logic that’s done by the GAL on the Daystar adapter.

If you take a close look at the SE/30 adapter that GAL is wired up different than on the IIsi adapter. Pin 19 of the GAL connects to /CENABLE. It is set to be low all the time in the fusemap. On the IIsi adapter /CENABLE connects to Pin 18 on that GAL which is only active if the memory controller in the IIsi wants to address an external cache.

Edited by Bolle

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1 hour ago, Bolle said:

...the TwinSpark but I don’t have one myself to check)

 

I have the original green version TS Adapter:

https://www.flickr.com/photos/66071596@N00/2406632009/in/album-72157633873937322/

 

I would be willing to ship it to you at my cost so long as you ship it back at your cost.

 

But now that I think about it, maybe I should ship you my Daystar Turbo040 too so you can have a look? :-)  We never came to a resolution in the following thread:

 

 

Let me know.

 

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On 6/11/2019 at 5:04 PM, Bolle said:

... Both of my PowerCaches are behaving the same in the SE/30, so it's not an issue with them. Someone with the original Daystar adapter would be helpful here now.

 

@BolleHere is what I could contribute: 

DSCN5750.pdf

Just let me know.

 

Not sure why uploading a JPEG did not work for me.

Edited by Udo.Keller

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7 hours ago, Bolle said:

@K Trueno a small jumper from C13 to C11 will do. Just make sure before that C13 isn’t connected anywhere else (it shouldn’t connect anywhere according to my info on the TwinSpark but I don’t have one myself to check)

I’d love to see that illustrated. Btw, I hooked up a better camera with a tripod, just in case more photos are needed.

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@Bolle Yup C13 goes no where as far as I can tell.  So I tried it!  Yaaaaah!  Full speed!  Fast stars are fast :-D

 

This is a huge discovery for Universal PowerCache users on the SE/30!

 

IMG_9830.thumb.JPG.6545aa844e6bd7d05e2b3b57ce9aa0f2.JPG

Screenshot_2019-06-13_07_14_03.thumb.png.6aed1f0b210587a10ef1787089aa159b.png

 

"Double your computer's speed with a paperclip".  That doesn't happen much these days!

 

 

@ktkm Here is a pic of my "jumper" :-D  Yeah its a paperclip right now.  I'll take more pics when I do it right this weekend, but there are markings on the PCB to for you to count (C is top row, there is 10 under the tenth pin, then  count over connect).     

 

 

IMG_8796.thumb.JPG.228f2c5c8cf430014d225ff17352ed21.JPG

Edited by K Trueno

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