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Franklinstein

601 processor replacement experiments

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I saw the summons just now, but Franklinstein pretty much wrote what I would have said, and more.  In summary:

 

1)  Bus speed doesn't matter, except for calculating potential CPU speeds.    All the processors you're looking at will run fine at the slow bus speeds that the Apple machines use.

 

2)  There are no L3 caches and no external cache support on the 750CX, FX and GX.    The 750 had support for an L2 cache.  If the L2 cache is internal, then there are no external Cache signal pins.

 

3)  As you concluded, bus multiplier is very important.    The early PPC750 only went up to 8X.  The 750L raised that to 10X.   The early G4/7400 only went up to 9X.    Later G4 models had higher multipliers, but I don't think that the later models are pin compatible with the PPC750.

 

4)  Only the 740 was pin compatible with the 603.   All other choices require a new board.

 

4)   If you're considering a brand new board, then later G4 chips are back on the table with higher multipliers, on-board cache, and potentially, external L3 cache.    But, Cost.

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Thanks much for the feedback. If I take anything like this into AI for hand routing playtime it's definitely gonna be a brand new CPU board design for the 1400. That processor card is by far the handiest testbed for this kinda crap in the 603e menagerie. Have I mentioned I have close to a two foot stack of the damn things and one arriving mid-week with my fourth G3 card on board? :lol:

 

Cost concerns you brought up had me looking up the CPU in my PartsBookAl/1GHz at work. It's the 7447A, its 21x multiplier takes it to 693MHz on a 33MHz bus and that'd be 1050MHz if it translates to an L2 board someone else might take on at some point. Same is true of an interstitial adaptation for a mobo ProcSwap that might be marginally less insane to take on. That route would certainly be a lot more flexible in terms of machines supported.

 

Signal to signal, 7447A <-> 603e looks like a hot mess and I've not even gotten down to GND in the alphabeticals. So I looked up iBooks on everymac thinking about the 900MHz G3s you mentioned, Franklinstein. But I found 800MHz, 933MHz and 1.0GHz G4 iBook models all using the 7457.  Haven't got to signal comparisons yet, but the chip's shit hot! Maybe that'd be cool shit? Must be a lower power/cooler running CPU because the multiplier tops out at 28x, which would be 933MHz on the 1400's 33MHz bus. [:D]

 

So, of course the signal compatibility cannot possibly work out. ::)

 

 

Edited by Trash80toHP_Mini

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At some point (I think the 7440/7450) the G4 no longer supported the 60x bus, only the MaxBus. The later chips could be run on a 60x-based machine but they required a bunch of adapter chips, which explains why there are very few >500MHz G4 upgrades for anything other than PCI Power Macs or UniNorth-based G4s. I did recently acquire a 700MHz Crescendo ZIF upgrade and it's huge, easily a 6" long card, with four QFPs and one BGA chip on it (in addition to the processor and two L3 cache chips).

 

All of the 750 variants support the 60x bus, so there are no bus-related problems with using a 750GX on an originally 603-based machine.

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For whatever its worth, Newer Technologies was able to essentially drop in a 740 G3 in place of a 603e processor on one of their blackbird CPU daughterboards because they are apparently fully pin-compatible, However, by the time their 740 G3 prototypes were completed, the interfaces for the CPU daughterboards were no longer being produced, so it was dead in the water.

 

Also, apparently in Japan, a guy was able to take a Newer Technology NuPower 167 Mhz CPU daughtercard, pop off the 603e, drop a 740 G3 in its place, and it worked without any difficulty.

 

From what I can tell, the PPC740L would be a drop-in replacement for the 603e.

 

Being a blackbird fan, I would like to see a 740 G3 run on a blackbird.

Edited by Paralel

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That Newer ProcSwap is great news. Not a practical approach for a first attempt though. Got sidetracked into the SE/30 morass for a bit last night right after work. An attitude adjustment later, I sat down to this and decided CPU availability was more relaxing than doing a block diagram of all transplants reported to have been successful. Dumb, idea every roll of the G4 dice came up came up snakeyes. That frustration sent me over to the G3 slot machine. There I hit for a nice jackpot. The cup ran over with 32,324 tokens PPC750FX-GB1033T PPC750FX BGA They're more expensive than @trag 's finds, but I don't foresee running out of a CPU similar to the 750LX used in Apple's iBook series from mid-1992 up to the G4 series.

 

666MHz is an appropriately devilish challenger for the Crescendo PB G3/466/1M in Beater, my grizzled 1400c RoadWarrior veteran. [}:)]

Edited by Trash80toHP_Mini

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edit: oopsie! The above should have read "similar to the 750FX used in the iBook G3 series and (possibly the same as?) the CPU in the end of series 900MHz iBook G3.

 

On 10/24/2018 at 4:45 PM, trag said:

Original PPC750 was in a 360 pin BGA (25mm X 25mm) with 8X maximum bus multiplier and selectable IO voltages of 3.3V, 2.5V or 1.8V.

 

PPC750L raised maximum bus multiplier to 10X.   These are the "copper" G3s.  360 pin BGA (25mm X 25mm)  

PPC740L     As above, but in 255 pin BGA (21 mm X 21 MM).    I guess this is the PPC603 compatible package, but not certain.

 

PPC750CX   Moved L2 cache to on-chip.   256K L2 cache on-chip.   Up to 10X bus multiplier.   256 pin BGA (27mm X 27mm)

 

PPC750FX   L2 cache increased to 512KB.  up to 20X bus multiplier.   292 pin BGA (21 mm X 21 mm)

 

PPC750GX, as 750FX except on-chip L2 cache increased to 1 MB

Dunno where a the 466MHz 750 on a 33MHz bus with off chip (backside) L2 on the PCB extension might fall into that chart. EveryMac's timeline data for that accelerator series would be:

 

Crescendo PB 333MHz 1/5/2000 release date jibes with PPC750L its 10x multiplier/external cache pincount

Crescendo PB 400MHz 7/19/2000 release date implied 12x multiplier breaks the 10x multiplier mold with external cache/pin count?

Crescendo PB 466MHz 2/15/2002 release date implies a 14x multiplier, also with backside L2 cache/pin count?

 

Release dates of the 750FX CPU and its speed bumps will need to be hashed out. It shows up mid-2002 on the 100MHz bus of the 600MHz iBook and tops out at 900MHz in the 2003 iBooks. That makes me wonder about bus multipliers and Apple's penchant for laming lower end models so as not to cannibalize high end model sales. But that's another, unrelated story/tangent/rabbit hole for someone else to explore.

_____________________________________________________________________________

 

My original question bringing on this line of research would be my curiosity about performance comparison of 512MB on die (frontside) L2 of the 750FX vs. 1MB external (backside) L2 on whatever the heck CPU is on the 2002 Crescendo PB 466MHz/1M I bought from Sonnet in 2005 to use the free WiFi of this smalltown downtown, NC?

 

So what should give better performance, 1M clock divided backside L2 or 512K of on die (frontside?) L2?

Bonus question: what the heck does Crescendo G3/PB 333/512k (1M) and 512k, 1 MB (backside) L2 in the EveryMac spec mean?

 

Edited by Trash80toHP_Mini

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5 hours ago, Trash80toHP_Mini said:

My original question bringing on this line of research would be my curiosity about performance comparison of 512MB on die (frontside) L2 of the 750FX vs. 1MB external (backside) L2 on whatever the heck CPU is on the 2002 Crescendo PB 466MHz/1M I bought from Sonnet in 2005 to use the free WiFi of this smalltown downtown, NC?

 

So what should give better performance, 1M clock divided backside L2 or 512K of on die (frontside?) L2?

Bonus question: what the heck does Crescendo G3/PB 333/512k (1M) and 512k, 1 MB (backside) L2 in the EveryMac spec mean?

 

The Crescendo PB 466/1M is most likely using an IBM 750L, the favored copper variant of the late-model 750 chips.

 

To quote Red Hill Technology, "more cache good; faster cache gooder." External SRAMs were kinda slow, especially as processors ticked up into the GHz range, so while you may be able to stick 2MB of backside cache on something, if it's only running at half processor speed (or less), it doesn't provide any more of a performance benefit than 1MB of on-die cache. In the 466/1M Crescendo, that 1MB of cache isn't running any faster than 2:1, more likely less (at least from stock; I think the control panel let you adjust that but stability wasn't guaranteed in all configurations). While this may be faster than a 750CX (it is 4x greater than the 750CX's 256k of cache), it will be the same as or slower than the 750FX's 512k. Rule of thumb: if a backside cache is </=2x the on-die cache of a comparable processor, the on-die variant will be the same or slightly faster. Especially if we're building new devices, the on-die variant would be preferable because there would be fewer devices to buy and would allow a much simpler PCB layout.

 

The Crescendo G3/PB 333 was probably available with a choice of 512k or 1MB models, depending on how much you wanted to spend. I'd bet there was a $50~80 difference between the two. The other option is that it was a long-lived product and it was upgraded from 512k to 1MB in later examples, much like the last of their Crescendo G4/PCI cards that used 1GHz+ chips when the slower ones were out of production.

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53 minutes ago, Franklinstein said:

The Crescendo PB 466/1M is most likely using an IBM 750L, the favored copper variant of the late-model 750 chips.

Thanks for the info, gotta see if I can get the ole' girl up and running to gimme any answer at all about what's under her yellow rubber panties.

Quote

To quote Red Hill Technology, "more cache good; faster cache gooder."

That's about what I was guessing, that 32K available CPU count is looking goodest about now.

 

Keep It Simple Stupid! is my mantra and it doesn't get any more simple than this:

 

1400-117-ProcCard-001.thumb.JPG.1f26fb287dbfc527f5f7df4b02db6b23.JPG

What the heck is that black Box?

 

This one I've already peeled off, but gotta clean it up to read it.

1300-117-ProcCard-000.thumb.JPG.2dba1df101d3fc5571cfee4d993914ea.JPG

 

Gotta find and get the continuity testing gear together to buzz a cable and then get busy with this little darling unless somebody has any serious reservations to bring up about my FX plans? Tomorrow I'll use the hot air station to pull the connectors off my partially denuded schematic development victim. That could make things a little easier. Connector pinout is the first step for wherever the wind blows this silliness.

 

PPC750FX-GB1033T PPC750FX BGA does mean 1033MHz CPU, no? 20x multiplier, here we go!

Edited by Trash80toHP_Mini

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603e is a 240 pin package with lots of redundancy of power and ground. Interconnects appear to total 160 pins with what's likely many fewer PWR/GND connections fanned out across the processors legs with load leveling and bypass caps aplenty.

 

CPU says XPC603EFE117MJ - Moto Logo  .  .  .  and what the heck is that black box with red sides?

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2 hours ago, Trash80toHP_Mini said:

.  .  .  and what the heck is that black box with red sides?

I'm 97% sure it's an inductor of some variety. Pretty much all of these things have at least one somewhere near the processor in the power supply section. 

 

The only concern regarding the FX I noted earlier: the package mounted atop an adapter may prove to be a little tall for a tight installation like this. Maybe measure the total height of the existing processor and thermal interface and then compare to the calculated height of the completed FX-on-adapter before pulling the trigger on anything crazy. You could still make it work but you'd need to engineer a new thermal solution in addition to the processor card. 

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That interchange about package thickness and available cubic in the 603e PowerBooks made the 1400 processor card the only logical lab varmint.

 

P1010002.thumb.JPG.77f7891b1a6420ba646f188934ac850b.JPG

The 1400s heat spreader is a removable 2mm aluminum assembly, not an integral magnesium frame as in the 2300c target machine for the theoretical interstitial adapter. Its thickness provides wiggle room of 1mm by way of milling away the surface.

 

P1010003.thumb.JPG.92f557418639926f76de558a22c4a3e5.JPG

That surface is a stamped indent on the assembly of about 4mm. The cubic it occupies under the top surface provides a last resort opportunity to mill a large opening for a massive copper adapter.

 

1400-117-ProcCard-002.JPG.39f93bd7bb349896ae29ddfa9609db7d.JPG

Was hoping for a better shot, but this shows the spatial relationships clearly enough.

 

As I said, that space makes the easily pulled CPU daughtercard of the 1400 the most logical choice for a 603e PowerBook upgrade that challenges anything available in the day. The 1400 was the only possibility for accelerator manufacturers outside of the 2400c with I've never even seen and  far too valuable to be used as a lab rat.

 

The stack of 1400s, my attachment to the machine that led to it and the  several extra logic boards and processor cards from the stack reduction project makes this no-brainer for something this insane. I've been working my way from PBX and the logic board connectors toward the PCMCIA cage/daughtercard interconnect on and off for 15 years now. The aim has always been to translate that half of the 1400'x split I/O bus into the Docking Connector of the Duo 2300c. Feasibility of physical installation of the 1400 PCMCIA assembly into the HDD bay of the 2300c was a done deal 15 years back! G3 insanity dovetails very nicely with that project on both sides of the shared PBX controllers in that Dynamic Duo.

 

dr. bob gave me a crash course on the basics of high frequency signalling after he finally gave in and admitted that the 1400 and 2300c are the same outside of the 1MB VRAM/ECSC upgrade of the 512K(?) VRAM/CSC Video Controller***** of the baseline 2300c. All other components of the 1400 were offloaded to the Docking Connector of the 2300c. Transplanting a 1400/G3 into the 2300c was the impossible dream of that full on manic episode. Guess what? 15 years and the dawn of the RaspBerry Pi/10x10cm SEEED PCB prototyping age and a partial return to sanity makes that proposition impractical, but maybe possible given interstitial adapter development?

 

1400-117-ProcCard-008.thumb.JPG.66c463e6f8fecc20b45dcf8d425183db.JPG

Note the "1600" printed on the lower left corner of the  (333MHz? )Sonnet card, what's that all about I wonder?

 

Another denizen of the 1400 stack reduction project box makes things a lot easier. Designing a breakout board PCB for the interboard connect is probably the first step on the journey. The PCB will have matching pads top and bottom for male/female header direct connection of harvested connectors and the pair will act as an interstertial breadboard interface. First for  when the time comes to play with the 750FX on a header matching protoboard. Hoping an underclock of the logic board enough that breadboarding will be possible while retaining function of the external video card.

 

1400-117-ProcCard-006.thumb.JPG.f47e1853e13641059bcdb196cd946e42.JPG

 

This Minimalist/1400 configuration mockup is a direct descendant of the original DuoDock based Minimalist/Duo 230 project box. The PCMCIA Card Cage/Daughtercard assembly will be removed on one left side of the CPU and the BookEndz Dock project box approach allows the breakout board to overhang KBD, speaker and LCD connectors at top and bottom. figuring out an adequate line driver/buffer setup for such a massive breadboard  prototyping contraption is something someone else will have to do for me.  Cubic aggregation building blocks and visual PCB trace schematic development I can do, but not the complicated electron pusher kinda stuff.

 

Adapter stack PCB development is my first order of business if this methodology proposal passes muster. Lil' help with that determination please. :huh:

 

 

*****maddog successfully gave the 2300c an ECSC transplant, but may have never gotten to or past feasibility studies for a 2300c VRAM upgrade. Full screen16bit on that gorgeous 2300c LCD would be very, very nice indeed! 

 

 

Edited by Trash80toHP_Mini

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23 hours ago, Franklinstein said:

To quote Red Hill Technology, "more cache good; faster cache gooder." External SRAMs were kinda slow, especially as processors ticked up into the GHz range, so while you may be able to stick 2MB of backside cache on something, if it's only running at half processor speed (or less), it doesn't provide any more of a performance benefit than 1MB of on-die cache

I'm not wanting to be a disturbance here; In fact I'm just keeping watch out of curiosity.

 

I believe more external backside cache (as opposite to less, faster on-chip) would be a bigger help, given a slow frontside bus with even slower memory will disproportionately bottleneck a (300mhz+?) chip at each FSB transaction. To me the trick should be to avoid as many FSB transactions as they're the worst case scenario (even more here). More backside cache is likelier to do so, and the L1 will still do its job..

Edited by rafthe030

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LOL! The more disruption in here the better, Hearing the "chioinnk" from across the room distrubed a half-nap I didn't really need.

 

External L2 on the backside is out of the question for anything in the soldered 603e PowerBook target range due to restricted cubic. Maybe if anything comes of this silliness we might see something along your line of thinking for the L2 Cache interface, but that's out in someone else's field of dreams.

 

That said, I'm confused by what you're saying. My understanding was that L1 is meant to keep the CPU's fingers off the cookies stored in the L2 jar and that the L2 cookie jar is meant to stall a headlong rush by the CPU out to the slow rate of production at cookie factory of main memory? Keeping as much of that kind of activity on the FSB would seem to be the thing to do to me. That said, there appear to be later versions with L2 on die and place additional clock divided L2 out on CPU card, or Logic Board between the die and 1x system bus memory.

 

Best case for the building blocks I've been able to line up thus far would be the 512K on die L2 of a 750FX running at 666MHz. Other options welcome!

 

I've got an 800MHz G4 accelerator card with what I assume must be L2 on die and external L3, but that's way out in BFE! :blink:

Edited by Trash80toHP_Mini

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I know the L2 interface is impossible :sadmac: It was just to give my version of the "So what should give better performance, 1M clock divided backside L2 or 512K of on die (frontside?) L2? " in one of your previous posts.

 

By mentionning the L1 I just meant the branch predictor and data caching mechanism will do their job and try to utilize the L2 and main memory, no matter how slow, the right way. And by "less frontside bus transactions" I meant less stalls from cache misses (not caching itself) since the bigger and heavier the dictionary, the more entries you can look up before having to boot up your sluggish PC to google what you're looking for.

 

A while ago I switched daily drivers from a Quicksilver G4 with 2x 1.6ghz 7447 w/ 512kb on-chip L2 to an MDD with 2 x 1.5ghz 7455 w/ 256kb on-chip L2 and 2mb L3 and I didn't know L3 made such a damn difference :I at times it feels like night and day

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The thing with external L2 caches is that they're not always half speed; sometimes it's much slower, 25% or less of processor clock. That's still faster than the memory bus (and doesn't have to go through the memory controller), granted, but significantly slower than the core frequency. If you could keep the backside cache at 2:1 and increase the size to whatever level you want, that would be one thing, but SRAMs don't generally keep up with processor speed and are expensive if they do, and also the 750 is max'd out at 1MB of external cache anyway. I did mention that generally it's a 2x difference in cache size when comparing internal vs. external, not 4x or more. Unless you're running the slowest SRAMs a 1MB external L2 will have more benefit than a 256k on-die cache, but the gap narrows when you're comparing 512k internal to 1MB external; I doubt you'd notice the difference at all between the latter unless you're running specifically-coded programs, like benchmarks, that can put the bulk of their routines in L2. 

 

In addition, more devices = more board space, more power consumption, and more heat generation, all of which are pretty big factors in portable applications.

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If anyone runs across a 750FX specific datasheet, tech sheet or best of all the user manual, that would be a big help. Everything I've found so far seems to be an indecipherable 740/750 morass. I have to try at work again, the filtering gets me hits I can't find at home. I absolutely HATE datasheetarchive.com and datasheetlib.com for munging up searches for everything about anything with irrelevance. The manuals versions of same are helpful/hurtful in random distribution.

 

The Shrier archive has info on PLL voodoo for the 1400, but no crystal swap overclocking info that might be used to slow the entire system down. Setting the multiplier to 1:1 will help, but I've got feasibility concerns about breadboarding a 33MHz processor interface. Does anyone have experience with breadboarding at 33MHz? I figure 16MHz or 8MHz would be more doable so long as I can retain clocked down Video expansion card function to run a multisync display. If my 33MHz worries are unfounded, please let me know. I look at this craziness as a logic analyzer crash course, so that makes brick wall collision/fail a positive goal! :approve:

 

Minimalist 1400 is installed in one of my project tool boxes so I can look at breakout board possibilities in 3D during downtime.

 

Do I recall a statement somewhere about a drop in G4 replacement for the 750FX?

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On 12/15/2018 at 7:52 PM, Trash80toHP_Mini said:

PPC750FX-GB1033T PPC750FX BGA does mean 1033MHz CPU, no? 20x multiplier, here we go!

 

No.   That signifies a 733MHz sort.

 

The two digits after "GB" are the "Performance Sort".

 

01 = 600 MHz

05 = 700 MHz

10 = 733 MHz

25 = 800 MHz

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Thanks for clearing that up, trag. That massive pole of CPUs would work great for the 1400's 666MHz limitation. On a 50MHz bus (very much if ever) a 15x multiplier would run them at a 2.4% overclocked 750MHz.

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9 hours ago, Paralel said:

Enjoy

[:)] Thanks so much! Took a look and laser printed some pages at work tonight. So far it's complicated or really bad news for anything but the 1400 and maybe the 2400? 750FX expects to find a formidable grid of decaps to be in place directly underneath on the solder side of the board.

 

750FX-DecouplingCapacitors.thumb.JPG.7c9f177a3a75819d562c101a7dc68349.JPG

 

I've never seen a 2400, but the 1400 card has zero problems providing for that grid. An interstitial adapter from 603e CQFP or BGA is another story entirely. Dunno how close the decaps need to be to where they're spec'd to be, but if they can't be moved to the periphery of the adapter, that's a brick wall. Thankfully the 750FX CPU is only a a tiny 21mm square. 603e CQFP pads make for an SMT interstitial PCB of about 37mm square leaving approx. 8mm on each side for relocating the scads of teensy capacitors above from the underside of the 750FX.

 

Signals are are on the periphery for the most part, which makes threading the signals into the grid from the interboard connectors on either side less than a totally daunting proposition.

 

750FX-V-G-Signals.thumb.JPG.d0f3aff9308373b4eee9b2c4fdedc51e.JPG

 

750FX-Ball-Placement-Pinout.thumb.JPG.36c308529c83f0660e03a199231bac57.JPG

 

Next up is finding out if signal differences between the 603e and 750FX will hose the project right out of the gate. Given signal compatibility the 1400 project looks socked in to maybe fair. CQFP interstitial adaptation for 2300c, 6400 and the rest looks socked in to zero visibility while flying through a mountain range.

 

BGA to BGA interstitial adaptation looks totally dependent upon how closely the bottom of a given 603e logic board resembles the decap map above. Numbers probably count more than locations, that's a whole lotta caplets. Basically it'd be rowing a dingy into a Nor'easter.

 

The fat lady is practicing scales while waiting for the signal compatibility verdict.  :mellow:

 

 

edit: massive pole of CPUs! :lol:

Edited by Trash80toHP_Mini

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Signal to Signal comparison came off pretty well, a few inconsistencies to research.

 

Looks like the 750FX may be last of the simple PLL clock multiplier setups. It has a variable setup for power saving modes, but MPC7447A doesn't seem to allow the multiplier to be set in hardware. Lovin' having that Migration from IBM 750FX to MPC7447A, Rev. 1 document available. Designing the 750FX board with provisions to do a 7447A "drop in" upgrade would be great, but methinks it better to relegate such dreams to a later revision. It's not like a 750FX board I do is gonna work given my lack of skills, but someone competent might follow up on the research at some point. :mellow:

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LOL! I transferred all my files for this and a related project into a plastic storage bin about three hours ago! What's the native Amiga CPU and ROM? 1400 ROM/Toolbox is for PPC, not 680x0.

 

Couldn't find package specs on on the Cyclone-III FPGA they used on Apollo? From various pics it looks like it might just fit, you've got me wondering about a PowerBook 100 processor card/accelerator again! :blink:

 

 

edit: iCrap, sounds a bit big in EQFP to fit with the SRAM on the card and support components for using it in a 5v environment.

--Plastic Enhanced Quad Flat Pack (EQFP), 144 pins, 22 mm x 22 mm

--BGA variant might work? 256-FBGA (17x17) is a bit better

Edited by Trash80toHP_Mini

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