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Compgeke

The Holy Grail of PCI Macs: Daystar Millennium Quad 604.

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1 hour ago, olePigeon said:

@Gorgonops Damn it!  Now I want that sooooo bad for my 486 PC.  Thanks a lot. :(

Heh. Google for "Everex STEP MegaCube", there are a number of threads about them on the VCF, et al. Owning one is apparently quite the status symbol among the select crowd that's impressed by 12 slot EISA 486/33s from 1991. :)

(That door over the drive bays has a *hydraulic damper* behind it, and it has a backlit LCD BIOS POST display on the front panel. Pretty boss...) ;)

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Maybe this is technological masochism on my part, but one of my first experiments after BeOS would be to try Debian 8 (Jessie) on the Quad 604.  The thought of something that modern on what's essentially a 20 year old high end workstation makes me giddy.  Maybe NetBSD too........

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Congratulations on your find!

You have a piece of history in your hands.

What first comes to mind is Steve Jobs yelling at executives and lawyers in Cupertino in 1997.

How ugly it is. This is what is killing Apple. The clone licences have to go. Is there no way to kill them?

 

It is such a pity that Andy Hertzfeld and Burrell Smith weren't massively enticed to stay on at Apple back in 1985. The Mac II could have & should have, IMHO, been a multi-processor machine back in 1987.

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On 10/8/2018 at 4:16 AM, Bolle said:

No need to compile the kernel yourself, you can download a precompiled 10.4.11 kernel that has the CPU check removed.

Not worth anything though if it doesn't see the additional CPUs.

Maybe it's hardware dependent or processor specific, but I would expect it to be able to see/handle at least two CPUs as there are dual-processor G4 machines (like the PM G4  Quicksilver DP 800 I have). Not sure how much it utilizes that hardware in general though.

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It's not so much that it has 2-4 processors but  the way Daystar implemented them. The old systems weren't native multi processor platforms so they did some trickery to get multiple CPUs working in the one slot. Apple used a different method of running multiple processors which was incompatible with nPower.

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On 10/15/2018 at 8:19 AM, Compgeke said:

It's not so much that it has 2-4 processors but  the way Daystar implemented them. The old systems weren't native multi processor platforms so they did some trickery to get multiple CPUs working in the one slot. Apple used a different method of running multiple processors which was incompatible with nPower.

 

I think that Daystar had to do some trickery to get four processors in one slot.   However, I'm pretty sure that the X500/X600 series of machines were designed with two processors per slot in mind.

 

Pins 19, 20, 21 and 81 of the CPU slot are PBR, PDBG, PBG and PINT, respectively.

 

Pins 55, 56, 57 and 58 are SINT, SBR, SDBG and SBG respectively.  

 

Where P = Primary and S = Secondary.

 

Full pinout is here:

https://www.prismnet.com/~trag/Apple_pinouts/CPU_Slot_Pinout

Edited by trag

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I have to admit I'm vaguely curious about the exact details of how things like interrupt routing and such works on Macs of that era with multiple CPUs, but short of trying to read the source code for the Linux kernel versions that supported SMP on them I'm not sure how to find those details. (I guess, come to think of it, I'm not sure exactly how the dual G4s work either.) That is one of the cool aspects of how Intel implemented SMP on the x86 line with their Multiprocessing Specification; the way the APIC bus worked the downstream hardware basically didn't have to care at all how many CPUs were present, and whether one CPU is doing all the work or if it's spread across all of them is entirely up to how you program said APICs.

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So, does the MP part work? Yes!. Need to use Mac OS 8.5 or older for it to properly work. I'll have to try and dig up something other than Powerfrax (the default sample program) to see how much of a different the MP really makes though.

 

n1SBxqL.jpg

 

jTOw53t.jpg

Edited by Compgeke

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I would love a multi processor 486 UNIX system but those are very rare (there should be some MP 386 systems as well from Compaq I think). Was hard enough to find a dual processor Pentium 1 board.

 

You are very limited in what OS you can use on those oddball beasts since they don't act like later MP systems.

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With regard to running OS X on this machine, it likely wouldn't see any CPU's that are not propagated in the device tree, but it should be possible to write a driver, hack the kernel, or maybe even do some Open Firmware hacks to enable the additional CPU's.

 

Really cool machine, I'm super jealous of your find, let me know if it's ever for sale.:beige:

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The multiprocessor setup on pre-G4 Macs is really weird and apparently wasn't implemented in a standard configuration since nothing except classic Mac OS running specially-coded software will use the extra processors. I don't have any in-depth technical info for them so I can only speculate as to how it works.

 

The Motorola MPC105/6/7 bridge chips support either a single processor and a directly-controlled L2 cache, or multiple processors with an externally-controlled L2 cache (implemented with an additional Motorola chip). If Apple's custom bridge chip(s) operate in this same manner, this may explain why they got MP working but only with weird software hacks: all Apple machines were set up to use a single processor with a directly-controlled L2 cache, so the additional processor had to be addressed and fed in a roundabout way.

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12 hours ago, Franklinstein said:

since nothing except classic Mac OS running specially-coded software will use the extra processors

There are old Linux mailing list postings that seem to indicate that SMP worked on those machines in some capacity, although I get the impression that it was never actually stable. Trying to get it to run today would likely be a really frustrating exercise in code archeology.

Didn't BEOS support SMP on multi-processor Macs?

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You kind of forget about BeOS these days, but BeOS is also weird because the BeBox was built with multiple 603 processors which were never designed to support an MP configuration. Be probably used the same sort of weird hackery that Apple did with their MP machines except they got proper SMP working.

 

No available Linux distro has proper, stable support for SMP on multiprocessor beige Macs; pretty much all of them don't even recognize the other processor. OS X, AFAIK, ignores the second processor regardless of what hacks are thrown at it.

 

The ANS is of course a completely different beast and I have no experience with any of them; A/UX and/or Linux may work fine in an SMP configuration on those but I can't say. Regardless, they're not Macs since they never ran the Mac OS.

 

Has anybody tried Rhapsody or A/UX on one of these?

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13 hours ago, Franklinstein said:

Be probably used the same sort of weird hackery that Apple did with their MP machines except they got proper SMP working.

The crucial difference when comparing Apple's MP machines and the BeBox is the 603 is fundamentally lacking support at the CPU hardware level to enable the cache coherency you need to enable true SMP. The BeBox gets around this by playing some really ugly games with software and its performance goes completely in the toilet if you ever try to switch a thread between the two cores.
 

13 hours ago, Franklinstein said:

No available Linux distro has proper, stable support for SMP on multiprocessor beige Macs; pretty much all of them don't even recognize the other processor.

Nonetheless it did at one point work on at least an experimental level; I've already posted one reference, here's another. I imagine they pulled support for those machines from later kernels because of some combination of them being "idiosyncratic" in terms of implementation compared to later machines (Linux is known to have trouble with pre-Pentium Pro SMP machines even though technically 486 and Pentium MP boards exist that comply with the Intel MP standard as documented) and the fact that there simply aren't enough of them in circulation to make the effort worthwhile. In particular I'm betting that it turned out to be really difficult to implement the new scheduler that came with the 2.6 kernel release on those old machines, assuming Apple didn't support I/O routing like Intel does with their APIC/MP hardware. (IE, the Beige hardware might be easy enough to make work with a "Big Lock" sort of SMP but is harder to make play nice with more sophisticated algorithms.)

 

 

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15 hours ago, Franklinstein said:

The ANS is of course a completely different beast and I have no experience with any of them; A/UX and/or Linux may work fine in an SMP configuration on those but I can't say. Regardless, they're not Macs since they never ran the Mac OS.

Where there dual-CPU ANSes? I honestly can't remember. I'm googling it and it looks like no?

In any case, almost all the chipset hardware in an ANS matches that of a Power Macintosh 9500. The two major differences are the ANS has a modified memory controller to support parity memory, and it uses a Cirrus Logic VGA chip instead of the standard Apple framebuffer ASIC. (I'm guessing the latter was to leverage an existing driver in AIX, some low-end CHIRP RS/6000 hardware used the same.) It's mostly a ROM block (and the weird video) that prevents MacOS from running on them.

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3 hours ago, Gorgonops said:

Where there dual-CPU ANSes? I honestly can't remember. I'm googling it and it looks like no?

In any case, almost all the chipset hardware in an ANS matches that of a Power Macintosh 9500. The two major differences are the ANS has a modified memory controller to support parity memory, and it uses a Cirrus Logic VGA chip instead of the standard Apple framebuffer ASIC. (I'm guessing the latter was to leverage an existing driver in AIX, some low-end CHIRP RS/6000 hardware used the same.) It's mostly a ROM block (and the weird video) that prevents MacOS from running on them.

 

There was one dual processor ANS that I know of and it had a unique ROM module (code was unique, not the physical module).  I was never able to get my hands on the ROM to copy it.

 

Correct, about the ANS being almost identical to a 9500.   The two datapath memory controllers are different to support parity, as you wrote.    The 9500 did not have built in video.    Apple video ASICs in the 7500/8500 lived on the CPU bus and so were equivalent in hierarchy to chips like Bandit and the main memory controller and bus arbiter, Hammerhead.   However, the ANS's video chip is implemented as a PCI device.  So it is just one more PCI device hanging on the PCI busses.

 

The other big differences are:

 

1)  the ROM code is different, of course.

2)  The PCI devices are arranged differently on the Bandit Bridges/PCI controllers.   On the 9500, the Grand Central chip and slots A - C are on Bandit 1 and slots D - F are on Bandit 2.    On the ANS, the Grand Central chip, two F&W SCSI chips, Cirrus Logic VGA chip and slots A - B are on Bandit 1.   Slots C - F are on Bandit 2.

3)   The interrupt mapping is a little different between the two machines.    Interrupts are (I hesitate to write "handled") routed through Grand Central for some kind of processing/registering, before the CPU gets an interrupt.   It looks like there are only 10 interrupts available on the Grand Central chip, or ten that aren't already being used by the IO of CURIO, the floppy controller and the MESH Fast SCSI controller.

 

Anyway, but there was one dual processor ANS out there.

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2 minutes ago, trag said:

The 9500 did not have built in video. 

Doh, I forgot about that. My faulty memory filled in that it had the same framebuffer as the 7/8xx's stashed on the board, but thinking about it at all I know that's wrong.


Just as an aside, the Developer Note that covers the 9600/200MP has this to say about it:

 

Quote

Dual Processor Configuration:

 

In the 9600/200MP model, two PowerPC 604e microprocessors are on the processor card.

With applications that support the new multiprocessor API, the MP configuration

provides up to 2 times the performance of the equivalent single-processor computers.

 

The operation of the dual-processor configuration is asymmetric multiprocessing. One

processor is the primary processor: it runs the Mac OS and handles interrupts from the

I/O systems. The second processor runs MP tasks as set up by the primary processor.

 

Unfortunately there's no documentation, not even a block diagram, in that document that hints at how they actually hang the multiple CPUs off the bus. Granted that's not the sort of information Apple used to give out about their machines, since they never intended for anyone to run alternate OSes on them. Therefore it's difficult to take much away from this statement, since the "Asymmetric" part may strictly refer to their particular software implementation rather than a limitation of the hardware.
 

Also, for shiznet and giggles I downloaded a random version of the Linux 2.4 kernel source. Here's what I found in arch/ppc/kernel/pmac_smp.c:

 

/*
 * SMP support for power macintosh.
 *
 * We support both the old "powersurge" SMP architecture
 * and the current Core99 (G4 PowerMac) machines.
 *
 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
 *
 * Support for DayStar quad CPU cards
 * Copyright (C) XLR8, Inc. 1994-2000
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

The comments in that file are interesting reading. Among other things it seems to say that the CPUs in those machines are not mapped to Open Firmware device tree entries, you have to use some not-totally-reliable probing of registers in the Hammerhead memory controller to try to determine if they're present and what exact flavor of "PowerSurge" you're dealing with. The init code for the "Core99" machines is far cleaner with a lot less "cross your fingers and pray you got it right" moments. Given that I can see why they ditched the PowerSurge code in Linux, and it also probably explains why OS X has *no idea* about those extra CPUs either. (OS X is *very* Open Firmware-centric.)

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... actually, it looks like the same code is at least still present in the source tree as of the latest stable, 4.18.16. At some point between that version of 2.4 and now added the following comment to the header, which is now in arch/powerpc/platforms/powermac/smp.c:
 

 * Note that we don't support the very first rev. of
 * Apple/DayStar 2 CPUs board, the one with the funky
 * watchdog. Hopefully, none of these should be there except
 * maybe internally to Apple. I should probably still add some
 * code to detect this card though and disable SMP. --BenH.

Whether it's still actually possible to enable this code as a configuration option or if the resulting kernel will just crash incessantly because there will be something else wrong above the platform driver level is of course utterly unknowable to me. If someone has one of these machines and a lot of time on their hands it might be an... interesting, experiment, to try to get a modern Linux distribution working on it.

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... replying to myself one more time, there's an interesting comment in the Peripheral Interrupt Controller code:
 

#ifdef CONFIG_PPC_PMAC32_PSURGE
        /* IPI's are a hack on the powersurge -- Cort */
        if (smp_processor_id() != 0) {
                return  psurge_secondary_virq;
        }

IPIs are "Inter-Processor Interrupts", and the platform support code also alludes to them being "not exactly straightforward to handle" on the PowerSurge architecture. If this was the root cause of the instability that was noted in those old mailing list posts about running Linux on these boxes that could well be why no out-of-the-box kernel today has SMP on this hardware enabled. I can only imagine the post-2.6 scheduler would exacerbate this problem... but, of course, I don't know anywhere enough about the situation to really say.

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A very faint memory says that the Ben Herrenschmidt mentioned above is the fellow who had the dual processor ANS, but that may just be a false association in my memory.

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