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ProtoCache1 - IIsi/SE/30 PowerCache Adapter Prototype Development

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Yeah, it's been quite an adventure.  Unfortunately, my programmer can't handle the latest (and only available) revision of the ATF16V8C, so I had to source some old Lattice GAL16V8s.  It'll be a little while before I receive them to test.

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Fabulous progress! :approve:

 

Is the I/O pinout listing for the GAL on the previous page complete? All other signals are a straight thru bus from MB to PDS via the crazy detours through CI, the IIci Cache Slot's oddball, one off pinout?

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Yeah, pretty much that's complete, other than missing pin17 and pin18, which I have now detailed below.  I still need to verify this with a complete blind re-check, and compare those results with these to be certain.  I will do that whilst I await my new PALs.

 

But yeah, pretty much all signaling is connected 1:1:1:1 between the PDS30, THRU, CACHE, and FPU slots, where they exist.  I wouldn't really call it a detour through the CI, because you have to think of it as a shared bus between all the connectors, rather than an origination or end point.  It's more like a rubber stamp application of an assertion all at once rather than piping that propagates through subsystems.

 

However, there are these important exceptions:

 

BGACK
The BGACK signal from PDS30 is connected to the PAL, pin 12.  It is connected 1:1 between the THRU and CACHE slots, but also held high through a 122Ω to +5V, and also connected to the PAL, pin1.  It is not a valid FPU signal, so it is absent there.
 
R/W
This signal is connected 1:1:1:1 between all four slots, but also connected to the PAL, pin2.
 
BG
/BG from the PDS30 is connected to the PAL, pin3.  It is connected 1:1 between the THRU and CACHE slots, also connected to the PAL, pin14.  It is not a valid FPU signal, so it is absent at the FPU.
 
DS
This signal is connected 1:1:1:1 between all four slots, but also connected to the PAL, pin4.
 
RSVD
This is a mystery signal derived from pin A1 on the PDS30 slot.  It's function is currently unknown.  This signal is connected 1:1 between the PDS30 and THRU slots, but also connected to the PAL, pin5.  It is not a valid signal on the CACHE or FPU slots, so obviously absent at those locations.
 
RESET
The /RESET signal is connected 1:1:1:1 between all four slots, but also held high through a 391Ω resistor to +5V.  It is also connected to the PAL, pin6.
 

A0

The /A0 signal is connected 1:1:1 between the PDS30, THRU, and CACHE slots.  It is not connected to the FPU.  Instead, A0 is connected to +5V at the FPU.  I thought that strange.  Why would /A0 would be connected to +5V and only at the FPU slot?  Well, after reading the 68882 user manual, I find that /A0 (along with /SIZE) is used to set the FPU operation mode.  If both signals are low, the FPU runs with an 8-bit data bus.  If both are high, it runs with a 32-bit data bus. And if /A0 is low, and /SIZE is high, it runs with a 16-bit data bus.  So that explains this anomaly quite well!

 

A1

The /A1 signal is connected 1:1:1:1 between all four slots, but also connected to the PAL, pin8.

 

A4

The /A4 signal is connected 1:1:1:1 between all four slots, but also connected to the PAL, pin9

 

CPUDIS

This signal is only valid on the CACHE slot.  It is held low with a 122Ω resistor to GND.  It is also connected to the PAL, pin11

 

D0

This signal is connected 1:1:1:1 between all four slots, but also connected to the PAL, pin15.

 

D3

This signal is connected 1:1:1:1 between all four slots, but also connected to the PAL, pin16.

 

CENABLE

This signal is only valid on the CACHE slot.  It is connected to the PAL, pin17.

 

CFLUSH

This signal is only valid on the CACHE slot.  It is connected to the PAL, pin18.

 

BERR
/BERR is connected 1:1:1 between the PDS30, THRU, and CACHE slots.  It's not a valid FPU signal, so it is absent there.  It is also held high through a 681Ω resistor to +5V.
 
CACHE

This one is a bit odd, but I toned it out several times to be sure.  Pin B2 on the PDS30 slot is identified as GND in the DCaDftMF.  And indeed, on the PDS30 slot, it is tied to GND.  However, on the THRU slot, it is not connected to GND.  Instead it is connected to the CACHE B40 pin, identified as the /CACHE signal.  I'm trying to figure out why this would be, but let me assure you, it is.

 

HALT

HALT is connected 1:1:1 between PDS30, THRU, and CACHE slots.  It is not a valid FPU signal, so it is absent there.  However, these signals are also held high through 681Ω resistor to +5V.

 

 

I created this diagram to help visualize the connections and their relationship with the PAL:

post-1870-0-54126300-1502169870_thumb.gif

 

I've been thinking about making one of toledogeek's Quick and Dirty flexable PDS extenders, but with a CACHE slot on the end and my PAL wired in.  Sure, I'd lose the PDS passTHRU, but it'd be a quick proof of concept to see if everything is in order.

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Hi...i am a new user here. In my case i wanted to mount two 601 cpu's via cpi's and two pds boards and one nubus.  I know I will probably have to upgrade or replace my PSU.  According to Daystar's marketing material the Turbo 601 was supposed to work in the SE/30 so I'm hoping the 6100's will too.  Will we have a choice in what we order?

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This board would be to fit a single IIci CACHE slot style accelerator in an SE/30, and have a PDS pass through as well.  Since it is basically a clone of the single PAL style DayStar card, whatever accelerators which work with that should work with this.  It will in no way provide a NuBus slot, or a way to use accelerators which are not of the IIci CACHE persuasion.

 

I do wonder if a card could be designed to provide two PDS slots and one IIci CACHE slot.  Iffy, because we rapidly loose space in the SE/30.

 

Perhaps two versions could be made.  A short one for mounting on top an ethernet adapter (modified with a wrong angle adapter), and another proper height version.

 

When this project is complete, the equations for PALs will be public domain, along with the pinouts of the slots, so anyone can design a card which fits their needs, and burn the GAL to support it.

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Some progress, and a hiccup...

 

I FINALLY successfully burned a Lattice GAL16V8D to replace the original MMI PAL16L8.  It works, kind of... The accelerator functions, but if anything is plugged into the PDS passthrough, it causes no boot and definitely no fun.  It works with the original PAL, so I know it is not a power supply issue.  Besides, I'm using an ATX power supply so I should have endless amps for multiple cards.

 

I need to check the voltages coming into the GAL and refer to the datasheets.  The Lattice part might have different input tolerances and output levels than the original MMI PAL part.  I may need to play with different resistor values.

 

Next steps:

 

Figure out why PDS passthrough is a show stopper.

Decide if I should use the old style GAL or switch to a modern and readily available FPGA such as the ICE40 series.

Start designing a board. 

 

 

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Could always switch to a 5v clpd. Just as fast and none of that 3.3->5v level shifting.

 

Quick edit before bed: Also as far as structure a PAL and a GAL should operate the same. I'd check the code again.

Edited by K55

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I do wonder if a card could be designed to provide two PDS slots and one IIci CACHE slot.

 

I was recently thinking about this baed on Gamba's multi-PDS page, as I removed my ethernet to fit in the Micron card. Dual PDS would be stellar.

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Hi...i am a new user here. In my case i wanted to mount two 601 cpu's via cpi's and two pds boards and one nubus.

 

Welcome aboard!

 

LOL! Been there, tried that. Another of my impossible dreams would be Project30.

 

NuBus on the SE/30 ought to be possible, the problem appears to be with how Bus Mastering Cards are handled on the its PDS. "Not well" or not as well as the IIsi, IIRC. The other gotcha is address mapping and Video memory conflict as in IIci adaptation for both SE/30 and IIsi. Someone with the chops to take a serious whack at that windmill (as zomb has done here) will need to get involved. I just set 'em up, don't have the expertise to actually do most of the projects I try to get rolling.

 

Takers? [;)]]'>

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I was recently thinking about this baed on Gamba's multi-PDS page, as I removed my ethernet to fit in the Micron card. Dual PDS would be stellar.

 

That ought to be doable, but the problem there is the limits of the PDS itself. The SE/30 is spec'd to drive just two inputs on the PDS, so line drivers/buffering will need to be designed and provided for on the adapter.

 

WAG: that'd be the other reason none of the Cache Accelerator Adapter mfr's provided a second passthru, Power limitations would be the first. ATX or booster pack required. :-/

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I'm running the code you got through wincupl and I'm able to compile it for independent devices but I'm getting compiler errors when compiling the output enable case for the 16v8. You forget brackets somewhere?

 

a1KI5cP.png

vs

nSgcOsg.png

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It's a little more complicated than that. The output enable equation listed there is actually dependent on the Pin13 (B1) output which is fed internally in the PAL and used in the .oe. What you see listed up there is the raw decompile from pa, and can't be used to recompile without replacement/reduction with the internally used equations. I thought I had done this correctly, but perhaps not.

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I've been plugging your equations (B0->B7) into the OE case in various ways to try and simplify it, but the end result is always a "true" or a "false". Unless there's more to it you're not showing, I don't see how this is working.

 

Edit: Without substitution that oe equation simplifies down to:

out= B0&I6 +B0&!I8 +B1&I9 +B3 +B4 +B6 +B7 +I0 +I1 +I2 +I3 +I4 +!B0&I8&!I9 +!B1&!I6 +!B1&!I8 +!B2 +!I5 +!I7;

 

Its clear to see that when the equations you need to substitute are:

B7 = 'b'1; /*eqns d'mgnd for simplicity*/
B6 = I5;
B5 = 'b'1;
B4 = 'b'1;
B3 = 'b'1;
B2 = I2 # I9;
B1 = I6 # I7 # I8;
B0 = I0 & !I9;

 

And if B7 = 1 and the output relies on B7, what should be my conclusion.... :-/

 

Not trying to get down on your work, I just like having something that can be reproduced easily :)

Edited by K55

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I will post my strategy concerning the .oe for you when I get home, perhaps a second set of eyes can help out.  Keep in mind, this is my first foray into PLD decoding, so don't think that I am a professional in any sense of the word.  :p

 

And also keep in mind, it isn't working yet.  Hence, the black screen of nothingness when a PDS is installed.

 

Edit:  Also, I don't think the output relies on B7.  Pin19 is unconnected on the circuit board, and is always high.  (which is practice, to keep levels from floating).

Edited by joethezombie

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Just wondering if my PLCC20 to DIP20 adapter might make sourcing compatible parts any easier. Looks like it plugs into your existing socket and is good to go with the more modern IC Package installed. Might proper PLCC parts be more readily available?

 

post-902-0-42446000-1497970309.jpg

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Joe, are you good on PALs and GALs?   I have a supply in the attic.  I can check my inventory.  I know I have some 16V8, but I can't remember what package(s) they're in (PLCC vs. DIP).  I might have both.

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Thanks for the offer trag!  I just bought a bunch off eBay a couple weeks ago so I'm set for now.   I just need to get back home and tinker with the logic.  I think we are nearly there with it.  I also have some of the good PLD experts from jammarcade.net helping me out with some ideas that could help this last hurdle.

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Have you looked at the overall operation of the adaptation in terms of which changes are doing what to the signal connections? Working out a truth table of known changes to logical operations of the PDS/IIci bus could be very useful. Extrapolating from there might help in figuring out what must be going on in the GAL from the operations they must be completing.

 

An analogy might be that you're stuck looking at the branches of the GAL tree and missing the forest of logical operations of the SE/30 and PowerCache which might indicate the necessary arrangement of the leaves on your branches?

 

Dunno, this is one long Peanut moment for me.

 

[/Jeff Dunham/Peanut]

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In another thread omidomo brought up an interesting point.

 

When I got my cards, I was getting the simasimac screen followed by the unhappy boot crash sound. Sakai-san informed me that the simasimac was normal as I had maxed out RAM, and the DayStar does it's own thing with the ROM. I was still not getting past the breaking sound with both cards, which lead me to purchasing the Hyper power supply from Artmix who had a few for sale at the time.

 

If Artmix was selling a turbocharged version of the SE/30 PSU, it's likely because their PowerCache/adapter/passthru card combo was taxing the rated power limits of the PDS. Might it be advisable to design provisions for PDS power cutout and a connector for an aux power supply or outright ATX conversions into our adapters where applicable? I'll have to hit the docs to find out what the power rating of the PDS would be.

 

ISTR some graphics cards requiring external power.

 

If we're making provisions for using all available interrupts and the PowerCache on the PDS, such seems advisable to me.

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Pulled from the Archive:

 

HPS_2006_A.jpg

 

  • Accelerator, enhanced power supply unit for driving large capacity HDD.
  • Although it was designed as a product version, due to various circumstances, it was decided to distribute it as a prototype final version. By example, for small volume production, reservation is necessary. (Please contact us for delivery date.)
  • With the ultra-large capacity of 145 W (MAIN) + 45 W (SWEEP) newly developed, it is possible to move 2 GB or more of the latest hard disk, 16 M SIMM, Turbo 040, etc. with leeway. (It is a special model which doubled the SWEEP of the conventional reinforced power supply, about twice the power of genuine power)
  • With no fan design, it achieves the same quietness and ultra low noise as the normal power supply. Moreover, by using the newly designed flyback transformer of HC specification, it becomes possible to obtain images with excellent visibility.
  • Avoid accelarator errors with phenomenal ripple characteristics.

 

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Sounds  to me like it's time to develop a prototype ATX conversion designed to fit within a stock PSU case.

 

It should re-purpose the original AC connectors/switch etc. as I'm doing with the SuperIIsi PSU. No cables involved there, but the sweep cable would be desoldered/redeployed as I'm using the and pass a pair of Multiconnector power cables straight through the grommet. The 300W FlexATX  PSU in my BG3 hack has a cable with one FDD and two MOLEX connectors.

 

Dunno what voltages are on the four pin ATX mobo connector extension offhand, but if one is 5V, that female or a PCB connector for FDD or SATA(?) ought to be easily sourced for the PowerCache Adapter.

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Sounds to me like it's time to develop a prototype ATX conversion designed to fit within a stock PSU case.

i did this with a flexatx power supply here:

https://68kmla.org/forums/index.php?/topic/229-beefier-power-supply-for-se30/?p=315680

 

interestingly enough, one of my se/30s came with a 3rd party power supply that was made for accelerators and video cards. i’m on mobile and can’t find my thread about it, but it was made in salt lake city.

 

Edit: found it:

https://68kmla.org/forums/index.php?/topic/29112-strange-power-supply-in-se30/?hl=party+power+supply

Edited by joethezombie

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Back to the PAL

Have you looked at the overall operation of the adaptation in terms of which changes are doing what to the signal connections?

Yes, I think everything is correct other than the cache enable. I theorize that the PAL is looking at the address range to determine if it is in the cache memory space, and asserting cenable based on that and some of the other states. I have a spiffy new 16 channel logic analyzer waiting for me at home, so I can get a better idea of what's happening when I get back.

 

My bet is if we were to drop the cache portion of the PAL, it would work fine for accelerators that have cache onboard, but cache-only cards wouldn't function. The artmix board for example doesn't look at the address space.

Edited by joethezombie

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Cool, figured you had, but just thought I'd ask if that didn't happen to be the case. [;)]]'>

 

Could the PAL be checking to see if the video subsystem is using memory mapped to Slot $E? My analysis of which Macs had which slots implemented/available against which had active or passive PowerCache adapters would indicate that your conflict would be polled in memory mapped to locations dedicated to the Video subsystems of the IIsi/SE30 which are implemented in PseudoSlot $E. Wherever $E is implemented, the adapters are active. Wherever $E is unimplemented, the adapters are passive with no known exceptions.

 

Differences between your IIsi form factor specific adapter and the Artmix/DiiMO SE/30 adapters might be evident. I know you and others have tested IIsi adapters in the SE/30, but has anyone tested an SE/30 form factor specific adapter in the IIsi? If that subset of the adaptation doesn't work in the IIsi, you may have found something very interesting/relevant to the current problem.

Edited by Trash80toHP_Mini

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