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Very nice polishing. I'd like to use whatever polish you used on my G4 Gigabit.

Ok great! I will send it when I get home.

If you have fusion or any other auto cad software that could read my files, I can send them to you that way you could see each of my measurements when you’re measuring

But I will try to soon! Maybe we can get this going again.

I had the design printed and prototype sent to me but the whole thing was off by like 1/4 an inch and I’m not sure how. I was so deterred that I haven’t picked it up since.

I haven’t exchanged chips yet

For the 550c when you go to the highest colors the full screen area isn’t used

One thing I wish was possible would be to somehow increase the VRAM even if that meant a desoldering project.

I've been wanting that processor for a while but they're so hard to come by! I've got a 550 with an Apple 603e 100MHz, which is in the FPGA format, and none of those go up higher than 133mhz if i replaced the chip. Does 9 run any different than 8.6 on 187MHz? I had to stay with 8.6. I do have an...

Update On my 1.6 Encore, I removed R 68 and bridged R 69 and this gave me a speed of 1.15. Anything higher than 1.6 would not give a chime. So if the above resistors hold true, then I assume the pattern would look like this below? These are 0 Ohm resistors so they are just bridges. I used...

It looks like the JTAG interface is at J3 and would need to be connected with flyleads. I wonder if this https://ebay.us/eMdcW1 would work. I'm not sure if that would reverse engineer it? re-looking at the R49-54 resistors I don't think they are part of PLL.

Looking at the datasheets, The PLL_CFG[0:5] would be 6 resistors (even though 5 is moot), IF it is true that the CPLD controls the frequency THEN the resistor should be set to "PLL Bypass" According to the PLL chart: that would mean "001100" which looks like it is feasible this could be...

if the PLL downstream of the PLD scenario were true, would the PLL logic still be similar to the 74xx logic

would Sonnet have made different PLD firmware for different speeds, or set the speed downstream (using PLL) of the PLD after it detects the bus?

hopefully without desoldering...

It looks like the PLD is Xilinx XC9536XV 7C and is the same on the different boards. Is there a way to reverse engineer with https://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html using the system debugger?

Super exciting! Does Sonnet's bus speed detection change how this works?

This is the 1.7 top side: this is the 1.6 top side: couldnt find a good picture of the 1.8

Hi everybody, I am wondering if the Sonnet Encore/ST G4 series can be overclocked similar to the Encore/MDX G4 Duet series as seen on http://macos9lives.com/smforum/index.php?topic=3523.0 by Knezzen and MacTron. Here is a picture of the underside of the 1.6GHz card: ...the 1.7 GHz card...

yes please!