Hi,
Just out of curiosity I was looking into how accelerators are designed for Macintosh SE. I know that some of them just plug into the socket instead of the original 68000 CPU and then the situation is clear.
But what is exactly happening with PDS accelerators when the onboard CPU stays in the socket?
Thanks for any references
Just out of curiosity I was looking into how accelerators are designed for Macintosh SE. I know that some of them just plug into the socket instead of the original 68000 CPU and then the situation is clear.
But what is exactly happening with PDS accelerators when the onboard CPU stays in the socket?
- Do they use the HALT signal?
- Do they use the BR/BG (Bus Request/Bus Granted) to halt the onboard CPU? It seems it is the case looking at some schematics and discussions here on 68kmla (e.g. this post) and various Amiga sources (e.g. https://majsta.com/modules.php?name=News&file=article&sid=17). That makes sense to me, but what about the DMA then? Do any SE-era peripherals actually take over the bus? What about e.g. network cards based on the DP8390* family?
Thanks for any references
