On the 7448, the 6th PLL signal is only used for factory testing and should always be pulled low, so if those cards use a 7448, you can bet your buttons that it's already being pulled low, and can safely be ignored. (Note that in that table of PLL configs, it's always a zero, indicating that every PLL configuration has it pulled low.)
But anyway, as Bolle said, if there are resistors to set the clock speed, their layout will not match the 74xx PLL_CFG but will rather just tell the PLD which target speed it should set. (And I doubt that the PLD would have a setting for PLL bypass.) And looking at the board, offhand it doesn't look like it would be set via pullup/pulldown, but rather using those resistors as a switch. (Basically the same thing that a DIP switch would do, but with SMD resistors instead.) So my guess is that it's the block of resistors that you initially highlighted (R66–69) and/or R44–48 that accomplish this. Probably both, since each block seems to connect to its own chip (at RP1 and RP2) which I assume has something to do with setting frequency. If we knew what chip that was (a clear extreme closeup shot via macro/magnifying lens or microscope would help) then we could track down its datasheet and learn a lot more. For example, it could be some kind of ASIC clock generator for all we know.
As it stands, with the information available, if it were me, I'd probably start by just taking the 1.6 board, configuring those resistors to match the 1.7 board (stuff R44, R66, and R67, and unstuff R68) and seeing if that does anything. If it works, try configuring it next to match the 1.8 board (unstuff everything except R67) and see if that works. I imagine it would work, since they seem to use the same PCB for all three products. Pushing beyond that could just be a matter of experimentation, or even just finding a datasheet for all we know.