Darn, I finally realized why my approach cannot work as-is. SBus has a somewhat 'modern' electrical interface, and the driving strength of the FPGA is enough to talk to the bus through the 74CB3T shifters (which are bidirectional pass-through, they don't drive the bus by themselves, they just make sure the FPGA doesn't get more than 3.3V on its pins). I thought I could just re-use the same principle, but I can't. Hence, darn.
NuBus has much, much higher driving requirements - way above what an Artix 7 can do. So now I need level-shifters with proper drivers, and those tend to be either bidirectional with weak drivers (won't work), or directional - meaning extra pins from the FPGA to set the direction; and proper grouping of signals to minimize the number of direction signals (without conflict in group - a nuisance is TM0 which is normally grouped with TM1 but can be used on its own as an intermediate 'ack' signal in block transfer...). And I'm not even sure that would work for the arbitration signals, as basically they are driven and sampled simultaneously - thus perhaps requiring external logic... which will need to talk to the 5V bus, the very problem we're trying to solve.
It still would work 'reasonably' easily by giving up on block transfers (which were only introduced in Quadra and so not universally useful even if I could figure out how to initiate one in software, and 2x mode isn't even supported to talk to main memory in Q700 and Q900 [1], no idea about newer Quadras) and on Master mode (no more need for arbitration!), thus needing just one direction pin for AD as I think everything else would be unidirectional (CLK, RESET and ID are always inputs, and for slave TM* and START are inputs while ACK and NMRQ are outputs). But it's not very satisfactory - and Master mode could be useful...
5V tolerant CPLD might do the trick (as PAL are no longer a thing), but that would add a lot of complexity...
[1] Coincidentally, while the Q700 and Q900 boast 2x mode but only for nubus-to-nubus, the SPARCstation 20 I use for SBus boast of 64-bits extended transfer but it's only for sbus-to-sbus ; apparently Sun and Apple agreed it was easier to upgrade the standard and tell 3rd-party what to do than actually upgrading the system controller itself
NuBus has much, much higher driving requirements - way above what an Artix 7 can do. So now I need level-shifters with proper drivers, and those tend to be either bidirectional with weak drivers (won't work), or directional - meaning extra pins from the FPGA to set the direction; and proper grouping of signals to minimize the number of direction signals (without conflict in group - a nuisance is TM0 which is normally grouped with TM1 but can be used on its own as an intermediate 'ack' signal in block transfer...). And I'm not even sure that would work for the arbitration signals, as basically they are driven and sampled simultaneously - thus perhaps requiring external logic... which will need to talk to the 5V bus, the very problem we're trying to solve.
It still would work 'reasonably' easily by giving up on block transfers (which were only introduced in Quadra and so not universally useful even if I could figure out how to initiate one in software, and 2x mode isn't even supported to talk to main memory in Q700 and Q900 [1], no idea about newer Quadras) and on Master mode (no more need for arbitration!), thus needing just one direction pin for AD as I think everything else would be unidirectional (CLK, RESET and ID are always inputs, and for slave TM* and START are inputs while ACK and NMRQ are outputs). But it's not very satisfactory - and Master mode could be useful...
5V tolerant CPLD might do the trick (as PAL are no longer a thing), but that would add a lot of complexity...
[1] Coincidentally, while the Q700 and Q900 boast 2x mode but only for nubus-to-nubus, the SPARCstation 20 I use for SBus boast of 64-bits extended transfer but it's only for sbus-to-sbus ; apparently Sun and Apple agreed it was easier to upgrade the standard and tell 3rd-party what to do than actually upgrading the system controller itself