It's 8MB <snip> Portable's 9MB capability <snip> RAM based Video Out card <snip> wonder if Sony reserved

From the Developer notes:
https://www.macdat.net/files/pdf/apple/developer_notes/powerbook_100.pdf
From the document, the PB 100 has some 70ns video RAM. An earlier page shows the block diagram for the PB 100:
But it's wrong here, the Internal Expansion connector should say "
A22-A1", because A19-1 only provides for 2MB. It's a typo, copied from the internal RAM address range. A22-A1 limits the RAM expansion to 8MB. Either that, or they mean there's 3 /CS signals + A19-A1 so that 3x 2MB of expansion RAM can be connected.
My personal opinion is that the early memory map on a Mac all the way to a Plus was dreadful. For the cost of a 74138, they could have put the ROM and I/O in the top 2MB (16MB/8) and subdivided further into 8x 256kB blocks for ROM, and all the devices (ROM, VIA, IWM, SCSI, Serial, + 5 spare for expansion?). Then 14MB Macs would have been possible.
Be that as it may, I held off on posting the "HARD NO" that
@croissantking let you down with (as softly as possible) in the first response.
I don't feel let down, I just don't think it's correct.
I still have my doubts about the inability to address additional memory in a non-contiguous fashion for the 68000.
A 68000 would be able to address all the remaining holes in the address space non-contiguously of course. What you can't do is expect the Plus's RAM slots to support 8MB easily. However, you could probably patch an additional address line from the 68000 to the 30-pin SIMM slots. 30-pin SIMMs have /CAS and /RAS address lines wired in, but have 12 address lines (A0-A11) and can individually address up to 16MB. However, A Mac plus has 2 SIMM slots so in theory it could address up to 32MB if the 68000 could (which of course it can't, unless you use the FC signals. Then you could have 16MB user space + 16MB supervisor space at least).
Instead, in the 4MB configuration, SIMM A0-A10 are mapped to A1-A11 (for /CAS) and A12-A2
1 (for /RAS) on the 68000's address bus. Not being totally familiar with the actual schematic, I suspect there's latches for /RAS and /CAS for A1-A11 and A12-A21; as well as data latches for D0-D15. Decode logic forces /WE high and D0-D15 read enable high if A22 NOR A23 [ /WE=MC68000.WE OR (A22 NOR A23); /RamRd=MC68000.RD OR (A22 NOR A23); ]. Note, the schematic will use different signal names.
In theory then I think that by patching A22 through to the A10 /RAS latch and by replacing (A22 NOR A23) with different decode logic (A23 OR (A22 AND NOT(A21 OR A20 OR A19 OR A18)) means 8MB would be supported, except for 256kB of RAM from $400000 to $43ffff . I don't know if screen memory would also be mirrored at the top of 8MB and 4MB if that was done; I don't know if the upper address bits are fully decoded for that.
<snip> RAM Disk boot <snip>
In the previous discussion, centred on the SE, it was suggested that the PDS card could be used to provide a RAM disk
Dunno, not likely, but might this longwinded drivel shake something loose in the noggin of one of our resident boffins?
So, I think that in my earlier post, I provided a software mechanism to access up to nearly 8MB and did some early experimentation. The next step, I think would be for me to modify the pce-mac emulator to support 8MB of RAM with a 25kB hole for ROM at $400000 and then change my AppGap app to an INIT which expanded the heap and allocated a fixed 256kB hole in the heap for RAM; which I'll call MacPlusROM (i.e. in the Finder or MultFinder it would look like there's a fixed application called MacPlusROM occupying 256kB in the middle of the application space).
-cheers from Julz