I'm not about to embark on this hack, but wanted to post the concept while I was thinking about it.
The only reason the 7100 is limited to 32MB SIMMs is because it runs the upper address lines for the SIMMs through a chip which "steals" them to create RAS lines to support more SIMM sockets.
The result of stealing those upper address lines is that 1) four SIMM sockets are supported instead of two (extra RAS lines) and 2) the maximum Bank size supported on each SIMM (2 banks per SIMM) is 16MB instead of 64MB.
In theory, one should be able to remove that RAS/address translation chip and jumper connections across the pads, so that just two SIMM sockets are active, but they will now support 64 MB per bank, or 128 MB per SIMM. This would raise the capacity to 264 MB.
I haven't looked in several years, but IIRC the chip is question is a 44 pin PLCC or something similar. The 7100 and 8100 have this chip. The 6100 does not. Otherwise the chipsets on the machines are identical,well, except for the lack of a NuBus controller on the 6100.
The only reason the 7100 is limited to 32MB SIMMs is because it runs the upper address lines for the SIMMs through a chip which "steals" them to create RAS lines to support more SIMM sockets.
The result of stealing those upper address lines is that 1) four SIMM sockets are supported instead of two (extra RAS lines) and 2) the maximum Bank size supported on each SIMM (2 banks per SIMM) is 16MB instead of 64MB.
In theory, one should be able to remove that RAS/address translation chip and jumper connections across the pads, so that just two SIMM sockets are active, but they will now support 64 MB per bank, or 128 MB per SIMM. This would raise the capacity to 264 MB.
I haven't looked in several years, but IIRC the chip is question is a 44 pin PLCC or something similar. The 7100 and 8100 have this chip. The 6100 does not. Otherwise the chipsets on the machines are identical,well, except for the lack of a NuBus controller on the 6100.