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Using a PDS slot instead of the 68k original socket doesn't make of a difference, maybe a bit more signal integrity issue but at the 68000 speed not really an issue. The PiStorm was designed for the Amiga, hence some of the choices. Using the approach to make a peripheral instead of a CPU is...

That's the idea behind the PiStorm and similar. The main issue is that without reconfigurable hardware, the bus must be bit-banged, and at the speed of a 68000 it's not trivial, and for faster things it becomes extremely difficult. Unlike some bit-banged protocols that can live with the...

@eharmon Thanks for sharing your experience!

Bit-banging NuBus might be possible, but stuff from that era are already somewhat fast and sensitive to timings. Using dedicated hardware through a FPGA or CPLD is likely to be a lot easier and much more reliable. One in a billion cycles with the wrong timings is already a crashing error every...

Depends :-) There's two HDMI output variants (part of the FPGA bitstream, so you need to reconfigure the FPGA to switch between the two): - one is 'true' hdmi (supports packets), so has an audio output going through to the display, but it can only do Full HD - lower resolutions are windowboxed -...

For Ethernet, the SEthernet/30 would do (either the original or my more compact variant), or any NuBus Ethernet, or indeed just remove a slot and hardwire a SEthernet/30 on the motherboard (slot might be easier for routing the mobo PCB though). The first issue with the LC slot is the 16 MHz...

The absolute bare minimum for a viable '030-or-later Mac is: (a) a CPU - a purely a money issue, as MC68030 and MC68040 are available for Rochester, plus all the usual sources of vintage chips (b) a memory controller and associated RAM - many alternate solutions available from SRAM to vintage...

Not easily. NuBus90 isn't actually "true" 20 MHz, it uses the 10 MHz NuBus clock (10 MHz 25%/75% duty cycle) for a lot of stuff, and only does data transfer using the 20 MHz (50%/50% duty cycle, so every other 20 MHz pulse matches a 10 MHz pulse). So it only improves performance for transfer of...

That's one option, yes. If you go that way, might as well go all the way to 6 slots plus the cache slot :) Basically, in the II, Apple defined 6 "slot area" (from $9 to $E, the 65k version of hexadecimal 0x9 to 0xE) and 6 associated interrupt lines for expansion devices, with one slot needed...

Pedantically, the actual FPGA itself isn't super expensive, even going for Full HD as in the *FPGA. But you're absolutely right the cost is high anyway, because you also need the PCB to carry the FPGA and all the extra required stuff :-( To support high resolution and high depth, you need a lot...

There's already some, both in the "fast, high-res, expensive, somewhat complex to setup, and purely as prototypes" (my own *FPGA range, complete with switchable resolution and depth up to Full HD in 24 bits), but also much easier to acquire/deploy based on an older chipset but for now only for...

I wouldn't call the coprocessor interface over-engineered - for the time it was quite good, and enabled a very clean programming model for ISA extensions. But (a) there wasn't enough justifiable use cases and (b) moore's law made it easy to simply integrate the most obvious use cases. Having the...

Nope, they don't, and neither do the internal MMU of the '030 (unlike the MC68851). CIR are only there to support the coprocessor interface at bus level, and so are only useful for external coprocessors running on the bus of a '020 or '030. For F-line instruction, in the '020 and '030 using an...

Do you have a SE/30 to test the PDS card in? The PDS of the SE/30 and IIsi are essentially compatible, but the faster clock of the IIsi (20 MHz vs. 16 MHz) means some card for the SE/30 won't work reliably in the IIsi - enough for the Mac to fail reading the ROM properly. This could be one of...

There's a design from Garrett's Workshop as well.

Having added 240 MiB to a IIsi with the IIsiFPGA (though reads are much slower than this, as the DDR3 is connected to the FPGA itself so requests go through it), you really don't want that much memory in there. No software needs (or even benefits from), that much memory, and it makes cold...

For those not familiar with Sun terminology, the "P4" is that familiar DIN connector you can see on the right underneath the booster, where the framebuffer would go [1]. From the schematics of the 3/60, it's basically a PDS for the MC68020 (so no /STERM). From some tracing and discussion for the...

Sorry, ambiguous notation on my side. I also meant 2-1-1-1 burst vs. 2 non-burst, which for 4 words in a cache line translate at 5 cycles total vs. 8 cycles total done back-to-back. Doing 2-2-2-2 burst will always be slower than 2-1-1-1 burst, and would be slower than 2 non-burst repeated four...

So it turns out to be true... I've seen design documents from SRAM and/or tag ram manufacturers claiming 2-1-1-1 burst was less efficient than 2-2-2-2 for fast L2 cache, complete with an explanation of the '030 behavior w/ and w/o burst. I've always wondered whether that was totally legit (it...

Mmm, I'm curious as to why /ECS is needed? 2-cycle is only possible with /STERM according to the documentation; while caches can't really do the tag lookup fast enough, they usually can do 2-cycle read by simply asserting /STERM immediately, and then forcing a bus retry if the tags don't match...