• Updated 2023-07-12: Hello, Guest! Welcome back, and be sure to check out this follow-up post about our outage a week or so ago.

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  1. M

    Adding 8 slots to my Compact Mac

    Thank you, that explain a bit. Memory map limits 60000 PDS (SE slot) to one and NuBus slots to 6, while available interrupts on the connector limits the SE/30 and IIsi expansion to 3 slots. So 4 (or even more so 8) slots feels a bit weird. Not impossible in theory, but that would require a lot...
  2. M

    128 pin PGA sockets for 68030s that don't suck?

    Paid €3.27 for 300 (allegedly, didn't count them...) on AliExpress. But yes, preci-dip is likely a better/easier option for 'standard' sockets - IMHO the interest lie more in things like the 'V' version of the 68040 in PGA package, whose socket is not listed in preci-dip's list of pin patterns.
  3. M

    128 pin PGA sockets for 68030s that don't suck?

    You could always make your own :-) Also, Preci-Dip 510-87-128-13-041101 is in stock at Mouser (France) and much less expensive than the Mill-Max. I haven't tried one, but the 510-83-068-10-061101 was fine for the '881/'882 in my PDS adapter.
  4. M

    Building PCB in Europe is soooo expensive...

    Yes, and it's quite frustrating. This particular manufacturer in Germany (aisler.net) used to have a service where they shipped parts along the PCB, but not assembled; for through-hole, it was convenient to avoids shipping costs on €2 worth of components. I did my MAC/VGA adapter and the custom...
  5. M

    Building PCB in Europe is soooo expensive...

    A simple PDS adapter with 2 slots for the IIci, so just 8 lines in the BoM for SMT (two for resistors, four for capacitors, small switch & a single 1G3157 IC switch). JLCPCB breakdown for 5 boards: Merchandise Total $48.87 Shipping $20.22 Customs duties & taxes $13.82 Grand Total: $82.91...
  6. M

    IIci etc. ATX to 10pin Adapter

    Those are the correct files, but the pick'n'place file only has the surface mounted components. The two plugs for power (J1, J2) and the switch (U1) I got separately and soldered by hand (they are listed in the BoM) - they hare through-holes. J2 is on the bottom side and by default JLCPCB only...
  7. M

    SEthernet and SEthernet/30: A new take on PDS Ethernet

    Turns out, space is really constrained - that 5V plug wouldn't fit, and I'm not sure an ethernet would would on the other side... so as not much power is needed, go for a micro-usb instead of the bulky plug, and rotate the Ethernet 90° so the cable has space inside the machine. @halkyardo Are...
  8. M

    IIsi NuBus adapter being weird but only with one specific video card

    I wouldn't expect a video device to need 12V, very surprised it did for such a critical function... so it works now in the IIsi?
  9. M

    IIsi NuBus adapter being weird but only with one specific video card

    The IIsi power supply and internal circuitry isn't great, so my suggestion it to check the voltage on the 5V rail in all three cases (no video and both video device). I would expect the Mac to go into self-reset rather than just hang, but it's an easy check so worth doing. Ideally you want at...
  10. M

    Supported PowerMac 6100 L2 sizes?

    I don't think the chips can do more than 1 MiB out-of-the-box as they don't have the necessary inputs. It might be possible to add external logic to support larger sizes, but then timings would become a major issue. 1MiB might be feasible, but I don't know of a reference design, and assembling...
  11. M

    LC III & LC 520/550 PDS slot compatibility

    Yes, the devnote for the 520 says it's the same. Page 30:
  12. M

    Supported PowerMac 6100 L2 sizes?

    After I posted that, I found some AliExpress vendor claiming they were selling the 66 MHz version for about $17 each. Between the unreliability of such claims, and the fact it would require being shipped to e.g. JLCPCB somehow for assembly (or be handled by someone able to solder BGA at 'home')...
  13. M

    Supported PowerMac 6100 L2 sizes?

    In theory, there's an alternate solution to the many chips implementation mentioned previously, but this would require a much larger budget... Motorola did produce an integrated 256 KiB L2 cache for the 60x bus, the MPC2605. You can use 1, 2 or 4 of them to produce a 256 KiB, 512 KiB, or 1 MiB...
  14. M

    SEthernet and SEthernet/30: A new take on PDS Ethernet

    OK thanks! I started from scratch in KiCad 5.1, where my PDS adapter was, so I redid the schematics there - still need to double-check them thouroughly... The footprints are also from from scratch, I'll also have to double-check but that should be OK, and JLCPCB's 2D/3D view provides a "final...
  15. M

    SEthernet and SEthernet/30: A new take on PDS Ethernet

    I see that you have betas on the way, do you consider the GitHub schematics "final"? As mentioned, I'm considering a much smaller form factor that could fit with a IIsiFPGA on a custom dual-PDS adapter (or stand-alone!). Current WiP looks like this: The 5V plug on the left is to power up the...
  16. M

    Fantasy M88100 Macs

    It is a nice CPU, and yes it's likely somewhat crippled by small caches - as most CPU would be, the L1 cache size being limited by area (almost any CPU without built-in L2) or by meeting L1 access latency requirements (almost everything since the introduction of the built-in L2). The 64-bits...
  17. M

    Fantasy M88100 Macs

    The MC88200 aren't CPUs, they are Cache/Memory Management Units for the MC88100 (the first implementation of the MC88000 architecture). The MC88100 doesn't have internal caches or MMU, aid it has two external 32-bits memory bus ("P-Bus"): one for instruction, one for data. Unifying that into a...
  18. M

    Fantasy M88100 Macs

    Multi-processor (either true SMP or some other schemes like the stuff implement in MP PPC machines under OS9) is mostly a software issue - you need the software to support it. And that means adapting the software to the quirks of the underlying hardware, and back in the days there was a lot of...
  19. M

    Interware Booster 30-SE50F Info Dump

    The documentation doesn't make it obvious in any one place, other sources are sometimes clearer. The important bit is a note right at the beginning of the UM in the preface: (emphasis mine). In the flowchart the negation of /DSACKx (or, in my case, /STERM) is also explicit, as it is in the...
  20. M

    Interware Booster 30-SE50F Info Dump

    Cost-cutting / didn't read the CPU manual properly (I'm betting the first!) Quoting from the '030 UM on asynchronous bus cycles: That's negate, not tri-state or deassert. The device should actively drive the signal to logic 0 (so +5V) before tri-stating for the next bus cycle, as relying on...
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