Insight on the 9500 180MP card

[CelGen]

I pulled this card from a a 9500 obviously enough (the 9500's case is hideous. I have no need for such an awful system) and have a few questions.
For starters I see that it clearly states it is for the 9500 only so it probably won't work in my 8600 and certainly not my 9600 (and regardless, a single 300 blows away a dual 180) would this be a ROM limitation or a speed limitation?
Another even more insane question is if the 604e's this thing has are pin compatible with the early revision G3 chips and if they are, would there be a ROM or speed issue with me swapping in say a set of 300's? I have the equipment to replace BGA components.

[MacJunky]

Put a PPC740 on a 6400/6500 board and tell/show us the results please!

[beachycove]

One works in my 8600. Quite why that "for 9500 only" is on the card is something of a puzzle. Cache speed, maybe?

[MacJunky]

It has something to do with the cache being on the card vs motherboard IIRC. At least that is what I recall hearing anyway.

[trag]

One works in my 8600. Quite why that "for 9500 only" is on the card is something of a puzzle. Cache speed, maybe?

The CPU slot wiring and the ROM code is the same in all of the x500 machines, so there's no reason it would not work in anything from a 7500 through a 9500. Probably work in all the x600s and the PowerSurge based clones as well.

[CelGen]

One works in my 8600. Quite why that "for 9500 only" is on the card is something of a puzzle

Okay then so then ROM and wiring wise at least there is no problem then. I looked at the crystal on the card and it's 45mhz so that means that to get 170mhz I'm currently running a 4x multiplier. To run something like dual 300mhz G3's, I'd dare say you replace the crystal with a 75mhz one and then swap in the two new chips and you should be good to go though I'm not sure what the ROM would say about the new processors, what the OS would need to do to actually use them as G3's and most importantly, if the system can handle that 75mhz crystal. I can't find the resistors that set the multiplier for the chips so I can't see if I can crank that up and then use a slower crystal.

[CelGen]

Hmm. Okay, so it seems that the 604e is exactly pin compatible with the 740 series G3 chips. It's unfortunate that all the G3 chips I have harvested so far from blue and white or beige hG3's all use the later 750 chips which are not pin compatible. I'm not exactly sure what 740 chips were used in other than possibly the "mainstreet" powerbook and I got rid of all my parts for those nasty laptops ages ago.

Edit: No, I am wrong. There was one XSC7400 350mhz chip I pulled but I don't remember what system I pulled that from. Regardless. I'm not sure if I can achieve a speed of 350mhz. That would require an 87.5mhz crystal with the 4X multiplier.

[CelGen]

No, I might be wrong again.
The part number (337-2572) of the ZIF card that this XSC7400 is on might in fact be a G4 processor whis is not what I need.
In fact, it seems that the first generation G4's used the model 7400 so that extra zero has confused me.
Okay, so in reality I still don't have even one 740 G3 chip. I just seem to be in reality swimming in a sea of 750 and 7400 G3 and G4 chips right now.

[beachycove]

Yes, I was not at all sure what you were on about.

There are 604e (manufactured later than Apple's use of them) that will fit in a G3 ZIF socket, but not the other way around.

[Bunsen]

The CPU slot wiring and the ROM code is the same in all of the x500 machines, so there's no reason it would not work in anything from a 7500 through a 9500.

Just in case it needs to be said- except the 5500 and 6500.

[Bunsen]

replace the crystal with a 75mhz one

That crystal also sets the motherboard clock speed. I don't like your chances.

[trag]

replace the crystal with a 75mhz one

That crystal also sets the motherboard clock speed. I don't like your chances.

Yes. You get the higher clock speeds by increasing the multiplying factor. Not by increasing the bus clock speed. In theory, it can be done either way, but the bus speed isn't going to work past about 60 MHz, and without knowing how to set the CLOCKID pins on the CPU socket, it may not work much above 45 MHz.

The PPC740 and PPC750 had clock multipliers up to 8X so there's plenty of room using higher clock multipliers.

The difference between the 740 and the 750 was that the 740 did not support the L2 backside cache and so did not have the hundred or so pins needed to interface with it. This is what made it possible to be pin compatible with the PPC603 (?) which (of course) also had no pins for a backside cache.

[CelGen]

Oh, so that crystal is not jsut for the CPU but for other parts of the system as well.
Hmm, yeah that would not work indeed.

[trag]

Oh, so that crystal is not jsut for the CPU but for other parts of the system as well.
Hmm, yeah that would not work indeed.

Correct. The clock for the whole system is on the CPU card. Change the CPU card; change the system clock.

The oscillator on the CPU card goes straight to a clock buffer MPC975 (IIRC) which replicates the clock seven or eight times. One of those clocks goes to the CPU. Six of the others go to the CPU card connector and thence, to the logic board, where they drive various logic board components.

Inside the CPU, the CPU clock multiplier is set, which multiplies the incoming clock signal by some factor between 1 & 8 (up to 10 on later PPC750, and up to 20 on much later PPC750cx, fx & gx).

The CPU clock multiplier is set by biasing pins on the CPU. This is usually set by installed resistors on the CPU card, but "adjustable" upgrades might have switches or jumpers for setting these pins. The later 750FX and 750GX had software settable CPU multipliers.

The CLOCKID pins on the CPU card tell the host system what bus speed to expect and so how to set its finer timing parameters. Poor understanding of CLOCKID pins led to the belief that everything should be run at 45MHz. Also, the fact that adjustable upgrades often didn't change the CLOCKID pins led to many many tests which clearly *showed* that a logic board could not run faster than 48 - 50 MHz.

However, if one had an upgrade such as the PowerLogix PowerBoostPro, one might reach as high as 62MHz bus speeds on x500 machines. In other words, the thing limiting logic board bus speeds to below 50MHz was not the logic boards, but the CPU upgrades which didn't handle the CLOCKID pins properly.

The PowerBoost Pro has a little microcontroller on board which adjusts the CLOCKID pins according to the bus clock speed setting to get best performance.

No, I don't know which CLOCKID setting correspond to which bus speeds. It is something I've meant to map out for years, but never have.

Here's the CPU socket pinout:

http://www.io.com/~trag/Apple_pinouts/CPU_Slot_Pinout

[Bolle]

Cant say it often enough http://www.flickr.com/photos/bolle_mac/2197370027
Strange thing is that when testing various G3 and G4 CPUs on the carrier with that setting only copper G3s did boot with that config. (all CPUs have been tested and are capable to run at the specified CPU clock)

I dont know what exactly this tells me but maximum stable bus speed was also connected to what cpu I drop in there even when settings remained the same.


Didnt know of the CLOCKID pins back then and dont know if my MACH Carrier sets them but i guess so. Question is can the used ZIF module mess with those CLOCKID settigns as not all CPUs seemed to work at 62mhz? for some i had indeed go down to 45mhz to get them to boot at all.

[trag]

maximum stable bus speed was also connected to what cpu I drop in there even when settings remained the same.

Didnt know of the CLOCKID pins back then and dont know if my MACH Carrier sets them but i guess so. Question is can the used ZIF module mess with those CLOCKID settigns as not all CPUs seemed to work at 62mhz? for some i had indeed go down to 45mhz to get them to boot at all.

It may also be the case that the PFD in the PLL of some CPUs does not support speeds above 50 MHz. The PFD is the component in the PLL which compares the incoming reference clock speed to a feedback signal from the CPU clock signal. There are various dividers in place so that the comparison makes sense. The PLL is the set of components which are used to set the clock multiplier and keeps the internal clock system of the chip reasonably steady.

This should be fairly easy to check by reading the datasheet, but they may not have provided that level of detail about the internal PLL.

[Bolle]

Well thing is all G3 ZIFs are made to run at least at 66mhz bus speed in a Gossamer or 100mhz in a yosi.