This is the kind of thing I'm doing:
module handshake_register
(
input wire underrun_n,
input wire write_data_ready,
input wire oe,
inout wire [7:0] data
);
assign data = oe == 1'b0 ? 8'bZZZZZZZZ : {write_data_ready, underrun_n, 5'b11111};
endmodule
Then there are multiple...